| Message ID | 20220902060342.151824-12-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Initial Meteorlake Support | expand |
On 01.09.2022 23:03, Radhakrishna Sripada wrote: > Display 14 and future platforms do not directly communicate to Pcode > via mailbox the SAGV bandwidth information. PM Demand registers are > used to communicate display power requirements to the PUnit which would > include GV point and mask value. > > Skip programming GV point and mask values through legacy pcode mailbox > interface. I agree to Matt's suggestion in v2 of this patch series, to move this patch to the future series where we would introduce the new pm_demand interface. It would make more sense there. > > Bspec: 64636 > Cc: Matt Roper <matthew.d.roper@intel.com> > Original Author: Caz Yokoyama > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b19a1ecb010e..69efd613bbde 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3923,6 +3923,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) > { > struct drm_i915_private *i915 = to_i915(state->base.dev); > > + /* > + * No need to update mask value/restrict because > + * "Pcode only wants to use GV bandwidth value, not the mask value." > + * for DISPLAY_VER() >= 14. > + */ > + if (DISPLAY_VER(i915) >= 14) > + return; > + My suggestion would be to remove the DISPLAY version check here and do it at the place where this function is invoked from. So for versions <14, intel_sagv_pre_plane_update can be called and for higher we need to implement the new pm_demand interface. > /* > * Just return if we can't control SAGV or don't have it. > * This is different from situation when we have SAGV but just can't > @@ -3943,6 +3951,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) > { > struct drm_i915_private *i915 = to_i915(state->base.dev); > > + /* > + * No need to update mask value/restrict because > + * "Pcode only wants to use GV bandwidth value, not the mask value." > + * for DISPLAY_VER() >= 14. > + * > + * GV bandwidth will be set by intel_pmdemand_post_plane_update() > + */ > + if (DISPLAY_VER(i915) >= 14) > + return; ditto > + > /* > * Just return if we can't control SAGV or don't have it. > * This is different from situation when we have SAGV but just can't Regards, Bala > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b19a1ecb010e..69efd613bbde 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3923,6 +3923,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); + /* + * No need to update mask value/restrict because + * "Pcode only wants to use GV bandwidth value, not the mask value." + * for DISPLAY_VER() >= 14. + */ + if (DISPLAY_VER(i915) >= 14) + return; + /* * Just return if we can't control SAGV or don't have it. * This is different from situation when we have SAGV but just can't @@ -3943,6 +3951,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); + /* + * No need to update mask value/restrict because + * "Pcode only wants to use GV bandwidth value, not the mask value." + * for DISPLAY_VER() >= 14. + * + * GV bandwidth will be set by intel_pmdemand_post_plane_update() + */ + if (DISPLAY_VER(i915) >= 14) + return; + /* * Just return if we can't control SAGV or don't have it. * This is different from situation when we have SAGV but just can't
Display 14 and future platforms do not directly communicate to Pcode via mailbox the SAGV bandwidth information. PM Demand registers are used to communicate display power requirements to the PUnit which would include GV point and mask value. Skip programming GV point and mask values through legacy pcode mailbox interface. Bspec: 64636 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)