diff mbox series

arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b

Message ID 20220718033145.792657-1-frattaroli.nicolas@gmail.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b | expand

Commit Message

Nicolas Frattaroli July 18, 2022, 3:31 a.m. UTC 
This adds the regulator node to the quartz64-b device tree,
and enables the PCIe 2 controller and combphy for it.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
 .../boot/dts/rockchip/rk3566-quartz64-b.dts   | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Heiko Stuebner Sept. 9, 2022, 11:10 p.m. UTC | #1 
On Mon, 18 Jul 2022 05:31:45 +0200, Nicolas Frattaroli wrote:
> This adds the regulator node to the quartz64-b device tree,
> and enables the PCIe 2 controller and combphy for it.

Applied, thanks!

[1/1] arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b
      commit: cd4e5f30f51f1066170a7c5f267cba6f062213e7

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
index 528bb4e8ac77..8e9cf3ac1c39 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
@@ -54,6 +54,18 @@  sdio_pwrseq: sdio-pwrseq {
 		power-off-delay-us = <5000000>;
 	};
 
+	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie_p";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
 	vcc5v0_in: vcc5v0-in-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_in";
@@ -113,6 +125,10 @@  &combphy1 {
 	status = "okay";
 };
 
+&combphy2 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -427,6 +443,14 @@  rgmii_phy1: ethernet-phy@1 {
 	};
 };
 
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_p>;
+	status = "okay";
+};
+
 &pinctrl {
 	bt {
 		bt_enable_h: bt-enable-h {
@@ -448,6 +472,16 @@  user_led_enable_h: user-led-enable-h {
 		};
 	};
 
+	pcie {
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	pmic {
 		pmic_int: pmic_int {
 			rockchip,pins =