diff mbox series

[net-next,v4] ravb: Add RZ/G2L MII interface support

Message ID 20220914175327.236988-1-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Netdev Maintainers
Headers show
Series [net-next,v4] ravb: Add RZ/G2L MII interface support | expand

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Context Check Description
netdev/tree_selection success Clearly marked for net-next
netdev/fixes_present success Fixes tag not required for -next series
netdev/subject_prefix success Link
netdev/cover_letter success Single patches do not need cover letters
netdev/patch_count success Link
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 0 this patch: 0
netdev/cc_maintainers success CCed 9 of 9 maintainers
netdev/build_clang success Errors and warnings before: 0 this patch: 0
netdev/module_param success Was 0 now: 0
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 0 this patch: 0
netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 34 lines checked
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Biju Das Sept. 14, 2022, 5:53 p.m. UTC 
EMAC IP found on RZ/G2L Gb ethernet supports MII interface.
This patch adds support for selecting MII interface mode.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * Dropped CXR35_HALFCYC_CLKSW1000 macro
 * Added CXR35_HALFCYC_CLKSW, CXR35_SEL_XMII and CXR35_SEL_XMII_RGMII
   macros.
v2->v3:
 * Documented CXR35_HALFCYC_CLKSW1000 and CXR35_SEL_XMII_MII macros.
v1->v2:
 * Fixed spaces->Tab around CXR35 description.
---
 drivers/net/ethernet/renesas/ravb.h      | 8 ++++++++
 drivers/net/ethernet/renesas/ravb_main.c | 8 +++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

Comments

Sergey Shtylyov Sept. 14, 2022, 6:24 p.m. UTC | #1 
On 9/14/22 8:53 PM, Biju Das wrote:

> EMAC IP found on RZ/G2L Gb ethernet supports MII interface.
> This patch adds support for selecting MII interface mode.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Dropped CXR35_HALFCYC_CLKSW1000 macro

   It's not macro...

>  * Added CXR35_HALFCYC_CLKSW, CXR35_SEL_XMII and CXR35_SEL_XMII_RGMII
>    macros.

   Neither are these...

> v2->v3:
>  * Documented CXR35_HALFCYC_CLKSW1000 and CXR35_SEL_XMII_MII macros.
> v1->v2:
>  * Fixed spaces->Tab around CXR35 description.
> ---
>  drivers/net/ethernet/renesas/ravb.h      | 8 ++++++++
>  drivers/net/ethernet/renesas/ravb_main.c | 8 +++++++-
>  2 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index b980bce763d3..b445da0fa578 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
[...]
> @@ -965,6 +966,13 @@ enum CXR31_BIT {
>  	CXR31_SEL_LINK1	= 0x00000008,
>  };
>  
> +enum CXR35_BIT {
> +	CXR35_HALFCYC_CLKSW	= 0xffff0000,

   Should come last...

[...]
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index b357ac4c56c5..421c8ff1ce1f 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -540,7 +540,13 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)
>  	/* E-MAC interrupt enable register */
>  	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
>  
> -	ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0);
> +	if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
> +		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
> +		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
> +	} else {
> +		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> +			    CXR31_SEL_LINK0);

   Hm... According to the RZ/G2LC manual, we still have to set CSR35.HALFCYC_CLKSW to
1000 even for RGMII... We probably need something more sophisticated here, like a flag
in the *struct* ravb_hw_info...

[...]

MBR, Sergey
Biju Das Sept. 14, 2022, 6:41 p.m. UTC | #2 
Hi Sergey,

> Subject: Re: [PATCH net-next v4] ravb: Add RZ/G2L MII interface support
> 
> On 9/14/22 8:53 PM, Biju Das wrote:
> 
> > EMAC IP found on RZ/G2L Gb ethernet supports MII interface.
> > This patch adds support for selecting MII interface mode.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * Dropped CXR35_HALFCYC_CLKSW1000 macro
> 
>    It's not macro...
> 
> >  * Added CXR35_HALFCYC_CLKSW, CXR35_SEL_XMII and CXR35_SEL_XMII_RGMII
> >    macros.
> 
>    Neither are these...
> 
> > v2->v3:
> >  * Documented CXR35_HALFCYC_CLKSW1000 and CXR35_SEL_XMII_MII macros.
> > v1->v2:
> >  * Fixed spaces->Tab around CXR35 description.
> > ---
> >  drivers/net/ethernet/renesas/ravb.h      | 8 ++++++++
> >  drivers/net/ethernet/renesas/ravb_main.c | 8 +++++++-
> >  2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/renesas/ravb.h
> > b/drivers/net/ethernet/renesas/ravb.h
> > index b980bce763d3..b445da0fa578 100644
> > --- a/drivers/net/ethernet/renesas/ravb.h
> > +++ b/drivers/net/ethernet/renesas/ravb.h
> [...]
> > @@ -965,6 +966,13 @@ enum CXR31_BIT {
> >  	CXR31_SEL_LINK1	= 0x00000008,
> >  };
> >
> > +enum CXR35_BIT {
> > +	CXR35_HALFCYC_CLKSW	= 0xffff0000,
> 
>    Should come last...

Ok, will do. If everyone ok with it.

> 
> [...]
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> > b/drivers/net/ethernet/renesas/ravb_main.c
> > index b357ac4c56c5..421c8ff1ce1f 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> > @@ -540,7 +540,13 @@ static void ravb_emac_init_gbeth(struct net_device
> *ndev)
> >  	/* E-MAC interrupt enable register */
> >  	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
> >
> > -	ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> CXR31_SEL_LINK0);
> > +	if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
> > +		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> 0);
> > +		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
> > +	} else {
> > +		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> > +			    CXR31_SEL_LINK0);
> 
>    Hm... According to the RZ/G2LC manual, we still have to set
> CSR35.HALFCYC_CLKSW to
> 1000 even for RGMII... We probably need something more sophisticated here,
> like a flag in the *struct* ravb_hw_info...

Strictly not required, as it is based on In-band Status. 

It is one of to do's in my backlog to add 
XMII selection for PHY which does not support In-band Status.


Cheers,
Biju
diff mbox series

Patch

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index b980bce763d3..b445da0fa578 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -189,6 +189,7 @@  enum ravb_reg {
 	PSR	= 0x0528,
 	PIPR	= 0x052c,
 	CXR31	= 0x0530,	/* RZ/G2L only */
+	CXR35	= 0x0540,	/* RZ/G2L only */
 	MPR	= 0x0558,
 	PFTCR	= 0x055c,
 	PFRCR	= 0x0560,
@@ -965,6 +966,13 @@  enum CXR31_BIT {
 	CXR31_SEL_LINK1	= 0x00000008,
 };
 
+enum CXR35_BIT {
+	CXR35_HALFCYC_CLKSW	= 0xffff0000,
+	CXR35_SEL_XMII		= 0x00000003,
+	CXR35_SEL_XMII_RGMII	= 0x00000000,
+	CXR35_SEL_XMII_MII	= 0x00000002,
+};
+
 enum CSR0_BIT {
 	CSR0_TPE	= 0x00000010,
 	CSR0_RPE	= 0x00000020,
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index b357ac4c56c5..421c8ff1ce1f 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -540,7 +540,13 @@  static void ravb_emac_init_gbeth(struct net_device *ndev)
 	/* E-MAC interrupt enable register */
 	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
 
-	ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0);
+	if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
+		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
+		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
+	} else {
+		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
+			    CXR31_SEL_LINK0);
+	}
 }
 
 static void ravb_emac_init_rcar(struct net_device *ndev)