| Message ID | 20220914095053.189851-2-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for J721e CPSW9G and SGMII mode | expand |
On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote: > Update bindings for TI K3 J721e SoC which contains 9 ports (8 external > ports) CPSW9G module and add compatible for it. > > Changes made: > - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. > - Extend pattern properties for new compatible. > - Change maximum number of CPSW ports to 8 for new compatible. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml > index 821974815dec..868b7fb58b06 100644 > --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml > +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml > @@ -57,6 +57,7 @@ properties: > - ti,am654-cpsw-nuss > - ti,j7200-cpswxg-nuss > - ti,j721e-cpsw-nuss > + - ti,j721e-cpswxg-nuss > - ti,am642-cpsw-nuss > > reg: > @@ -111,7 +112,7 @@ properties: > const: 0 > > patternProperties: > - "^port@[1-4]$": > + "^port@[1-8]$": > type: object > description: CPSWxG NUSS external ports > > @@ -121,7 +122,7 @@ properties: > properties: > reg: > minimum: 1 > - maximum: 4 > + maximum: 8 > description: CPSW port number > > phys: > @@ -181,6 +182,21 @@ required: > - '#size-cells' > > allOf: > + - if: > + not: > + properties: > + compatible: > + contains: > + const: ti,j721e-cpswxg-nuss > + then: > + properties: > + ethernet-ports: > + patternProperties: > + "^port@[5-8]$": false > + properties: > + reg: > + maximum: 4 Your indentation is off. 'properties' here is under patternProperties making it a DT property. > + > - if: > not: > properties: > @@ -192,6 +208,9 @@ allOf: > ethernet-ports: > patternProperties: > "^port@[3-4]$": false > + properties: > + reg: > + maximum: 2 Same here. > > additionalProperties: false > > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote: > Update bindings for TI K3 J721e SoC which contains 9 ports (8 external > ports) CPSW9G module and add compatible for it. > > Changes made: > - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. > - Extend pattern properties for new compatible. > - Change maximum number of CPSW ports to 8 for new compatible. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) What's the base for this patch? It didn't apply for me. Run 'make dt_binding_check'. It should point out the issue I did. If not, let me know. Rob
Hello Rob, On 14/09/22 21:50, Rob Herring wrote: > On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote: >> Update bindings for TI K3 J721e SoC which contains 9 ports (8 external >> ports) CPSW9G module and add compatible for it. >> >> Changes made: >> - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. >> - Extend pattern properties for new compatible. >> - Change maximum number of CPSW ports to 8 for new compatible. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- >> 1 file changed, 21 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml >> index 821974815dec..868b7fb58b06 100644 >> --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml >> +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml >> @@ -57,6 +57,7 @@ properties: >> - ti,am654-cpsw-nuss >> - ti,j7200-cpswxg-nuss >> - ti,j721e-cpsw-nuss >> + - ti,j721e-cpswxg-nuss >> - ti,am642-cpsw-nuss >> >> reg: >> @@ -111,7 +112,7 @@ properties: >> const: 0 >> >> patternProperties: >> - "^port@[1-4]$": >> + "^port@[1-8]$": >> type: object >> description: CPSWxG NUSS external ports >> >> @@ -121,7 +122,7 @@ properties: >> properties: >> reg: >> minimum: 1 >> - maximum: 4 >> + maximum: 8 >> description: CPSW port number >> >> phys: >> @@ -181,6 +182,21 @@ required: >> - '#size-cells' >> >> allOf: >> + - if: >> + not: >> + properties: >> + compatible: >> + contains: >> + const: ti,j721e-cpswxg-nuss >> + then: >> + properties: >> + ethernet-ports: >> + patternProperties: >> + "^port@[5-8]$": false >> + properties: >> + reg: >> + maximum: 4 > > Your indentation is off. 'properties' here is under patternProperties > making it a DT property. > >> + >> - if: >> not: >> properties: >> @@ -192,6 +208,9 @@ allOf: >> ethernet-ports: >> patternProperties: >> "^port@[3-4]$": false >> + properties: >> + reg: >> + maximum: 2 > > Same here. Thank you for reviewing the patch. Sorry for the indentation errors. I will fix them in the v2 series. Regards, Siddharth.
Hello Rob, On 14/09/22 21:53, Rob Herring wrote: > On Wed, Sep 14, 2022 at 03:20:46PM +0530, Siddharth Vadapalli wrote: >> Update bindings for TI K3 J721e SoC which contains 9 ports (8 external >> ports) CPSW9G module and add compatible for it. >> >> Changes made: >> - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. >> - Extend pattern properties for new compatible. >> - Change maximum number of CPSW ports to 8 for new compatible. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- >> 1 file changed, 21 insertions(+), 2 deletions(-) > > What's the base for this patch? It didn't apply for me. I was working with linux-next tagged: next-20220913. > > Run 'make dt_binding_check'. It should point out the issue I did. If > not, let me know. Sure. Thank you. Regards, Siddharth.
diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index 821974815dec..868b7fb58b06 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -57,6 +57,7 @@ properties: - ti,am654-cpsw-nuss - ti,j7200-cpswxg-nuss - ti,j721e-cpsw-nuss + - ti,j721e-cpswxg-nuss - ti,am642-cpsw-nuss reg: @@ -111,7 +112,7 @@ properties: const: 0 patternProperties: - "^port@[1-4]$": + "^port@[1-8]$": type: object description: CPSWxG NUSS external ports @@ -121,7 +122,7 @@ properties: properties: reg: minimum: 1 - maximum: 4 + maximum: 8 description: CPSW port number phys: @@ -181,6 +182,21 @@ required: - '#size-cells' allOf: + - if: + not: + properties: + compatible: + contains: + const: ti,j721e-cpswxg-nuss + then: + properties: + ethernet-ports: + patternProperties: + "^port@[5-8]$": false + properties: + reg: + maximum: 4 + - if: not: properties: @@ -192,6 +208,9 @@ allOf: ethernet-ports: patternProperties: "^port@[3-4]$": false + properties: + reg: + maximum: 2 additionalProperties: false
Update bindings for TI K3 J721e SoC which contains 9 ports (8 external ports) CPSW9G module and add compatible for it. Changes made: - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. - Extend pattern properties for new compatible. - Change maximum number of CPSW ports to 8 for new compatible. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)