diff mbox series

[net-next,v2,4/5] net: mediatek: sgmii: set the speed according to the phy interface in AN

Message ID 20220919083713.730512-5-lynxis@fe80.eu (mailing list archive)
State New, archived
Headers show
Series net: mediatek: sgmii stability | expand

Commit Message

Alexander Couzens Sept. 19, 2022, 8:37 a.m. UTC
The non auto-negotioting code path is setting the correct speed for the
interface. Ensure auto-negotiation code path is doing it as well.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
---
 drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

Comments

Russell King (Oracle) Sept. 19, 2022, 11:15 a.m. UTC | #1
On Mon, Sep 19, 2022 at 10:37:11AM +0200, Alexander Couzens wrote:
> The non auto-negotioting code path is setting the correct speed for the
> interface. Ensure auto-negotiation code path is doing it as well.

While I see the logic in doing this in the autoneg path, if you look
at mtk_pcs_config(), you'll notice that this code you're adding is
unreachable.

If interface is PHY_INTERFACE_MODE_2500BASEX, then we will call
mtk_pcs_setup_mode_force(). We only call mtk_pcs_setup_mode_an() for
the PHY_INTERFACE_MODE_SGMII case when in-band mode is selected, so
this can become:

	regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
	val &= ~RG_PHY_SPEED_MASK;
	regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);

Thanks.
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
index 6f4c1ca5a36f..4c8e8c7b1d32 100644
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
@@ -21,13 +21,20 @@  static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
 }
 
 /* For SGMII interface mode */
-static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
+static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface)
 {
 	unsigned int val;
 
 	/* PHYA power down */
 	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
 
+	/* Set SGMII phy speed */
+	regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
+	val &= ~RG_PHY_SPEED_MASK;
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val |= RG_PHY_SPEED_3_125G;
+	regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
+
 	/* Setup the link timer and QPHY power up inside SGMIISYS */
 	regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
 		     SGMII_LINK_TIMER_DEFAULT);
@@ -112,7 +119,7 @@  static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
 	if (interface != PHY_INTERFACE_MODE_SGMII)
 		err = mtk_pcs_setup_mode_force(mpcs, interface);
 	else if (phylink_autoneg_inband(mode))
-		err = mtk_pcs_setup_mode_an(mpcs);
+		err = mtk_pcs_setup_mode_an(mpcs, interface);
 
 	return err;
 }