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[0/3] hw/riscv: opentitan: Fixup resetvec issues

Message ID 20220914101108.82571-1-alistair.francis@wdc.com (mailing list archive)
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Series hw/riscv: opentitan: Fixup resetvec issues | expand

Message

Alistair Francis Sept. 14, 2022, 10:11 a.m. UTC 
The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
ROM flow. This series makes it more configurguable from the command line
and fixes the default.

Alistair Francis (3):
  target/riscv: Set the CPU resetvec directly
  hw/riscv: opentitan: Fixup resetvec
  hw/riscv: opentitan: Expose the resetvec as a SoC property

 include/hw/riscv/opentitan.h |  2 ++
 target/riscv/cpu.h           |  3 +--
 hw/riscv/opentitan.c         |  8 +++++++-
 target/riscv/cpu.c           | 13 +++----------
 target/riscv/machine.c       |  6 +++---
 5 files changed, 16 insertions(+), 16 deletions(-)

Comments

Alistair Francis Sept. 19, 2022, 11:33 p.m. UTC | #1 
On Wed, Sep 14, 2022 at 8:11 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
> ROM flow. This series makes it more configurguable from the command line
> and fixes the default.
>
> Alistair Francis (3):
>   target/riscv: Set the CPU resetvec directly
>   hw/riscv: opentitan: Fixup resetvec
>   hw/riscv: opentitan: Expose the resetvec as a SoC property

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  include/hw/riscv/opentitan.h |  2 ++
>  target/riscv/cpu.h           |  3 +--
>  hw/riscv/opentitan.c         |  8 +++++++-
>  target/riscv/cpu.c           | 13 +++----------
>  target/riscv/machine.c       |  6 +++---
>  5 files changed, 16 insertions(+), 16 deletions(-)
>
> --
> 2.37.2
>