| Message ID | 20220911235945.6635-3-andre.przywara@arm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: sunxi: h616: Add USB support | expand |
On 12/09/2022 01:59, Andre Przywara wrote: Thank you for your patch. There is something to discuss/improve. > clocks: > + minItems: 4 > items: > - description: USB OTG PHY bus clock > - description: USB Host 0 PHY bus clock > - description: USB Host 1 PHY bus clock > - description: USB Host 2 PHY bus clock > + - description: PMU clock for host port 2 > > clock-names: > + minItems: 4 > items: > - const: usb0_phy > - const: usb1_phy > - const: usb2_phy > - const: usb3_phy > + - const: pmu2_clk > > resets: > items: > @@ -98,6 +102,21 @@ required: > > additionalProperties: false > > +if: Please enclose it within allOf: block. Helps to reduce indentation changes later when this grows. > + properties: > + compatible: > + contains: > + enum: > + - sun50i-h616-usb-phy > + > +then: > + properties: > + clocks: > + minItems: 5 > + > + clock-names: > + minItems: 5 I assume other variants do not have this clock? If correct, then: else: clocks: maxItems: 4 and the same for clock-names > + > examples: > - | > #include <dt-bindings/gpio/gpio.h> Best regards, Krzysztof
On 12-09-22, 00:59, Andre Przywara wrote: > The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves > some resources from port 2's PHY and HCI IP. In particular the PMU clock > for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL > register of port 2. To allow each USB port to be controlled > independently of port 2, we need a handle to that particular PMU clock > in the *PHY* node, as the HCI and PHY part might be handled by separate > drivers. > > Add that clock to the requirements of the H616 PHY binding, so that a > PHY driver can apply the quirk in isolation, without requiring help from > port 2's HCI driver. This is phy binding patch and not a usb one, pls fix the subystem name for patch > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > .../phy/allwinner,sun8i-h3-usb-phy.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml > index e288450e0844..3a3168392597 100644 > --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml > @@ -36,18 +36,22 @@ properties: > - const: pmu3 > > clocks: > + minItems: 4 > items: > - description: USB OTG PHY bus clock > - description: USB Host 0 PHY bus clock > - description: USB Host 1 PHY bus clock > - description: USB Host 2 PHY bus clock > + - description: PMU clock for host port 2 > > clock-names: > + minItems: 4 > items: > - const: usb0_phy > - const: usb1_phy > - const: usb2_phy > - const: usb3_phy > + - const: pmu2_clk > > resets: > items: > @@ -98,6 +102,21 @@ required: > > additionalProperties: false > > +if: > + properties: > + compatible: > + contains: > + enum: > + - sun50i-h616-usb-phy > + > +then: > + properties: > + clocks: > + minItems: 5 > + > + clock-names: > + minItems: 5 > + > examples: > - | > #include <dt-bindings/gpio/gpio.h> > -- > 2.35.3
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index e288450e0844..3a3168392597 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -36,18 +36,22 @@ properties: - const: pmu3 clocks: + minItems: 4 items: - description: USB OTG PHY bus clock - description: USB Host 0 PHY bus clock - description: USB Host 1 PHY bus clock - description: USB Host 2 PHY bus clock + - description: PMU clock for host port 2 clock-names: + minItems: 4 items: - const: usb0_phy - const: usb1_phy - const: usb2_phy - const: usb3_phy + - const: pmu2_clk resets: items: @@ -98,6 +102,21 @@ required: additionalProperties: false +if: + properties: + compatible: + contains: + enum: + - sun50i-h616-usb-phy + +then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + examples: - | #include <dt-bindings/gpio/gpio.h>
The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves some resources from port 2's PHY and HCI IP. In particular the PMU clock for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL register of port 2. To allow each USB port to be controlled independently of port 2, we need a handle to that particular PMU clock in the *PHY* node, as the HCI and PHY part might be handled by separate drivers. Add that clock to the requirements of the H616 PHY binding, so that a PHY driver can apply the quirk in isolation, without requiring help from port 2's HCI driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- .../phy/allwinner,sun8i-h3-usb-phy.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)