| Message ID | 20220923114658.8286-1-allen-kh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mt8192: Add vcodec lat and core nodes | expand |
On Fri, Sep 23, 2022 at 7:47 PM Allen-KH Cheng <allen-kh.cheng@mediatek.com> wrote: > > Add vcodec lat and core nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> > --- > This patch is based on matthias.bgg/linux.git, v6.0-next/dts64 > [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] > --- > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 6b20376191a7..aa6524948e7c 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1449,6 +1449,66 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; > }; > > + vcodec_dec: vcodec-dec@16000000 { The device node name should be generic, so maybe "video-codec@"? > + compatible = "mediatek,mt8192-vcodec-dec"; > + reg = <0 0x16000000 0 0x1000>; > + mediatek,scp = <&scp>; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0x16000000 0 0x26000>; > + > + vcodec_lat: vcodec-lat@10000 { Same here. > + compatible = "mediatek,mtk-vcodec-lat"; > + reg = <0x0 0x10000 0 0x800>; > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > + }; > + > + vcodec_core: vcodec-core@25000 { Same here. ChenYu
Hi Chen-Yu, Thanks for the suggestion and test. The following version will fix the node's name. BRs, Allen On Mon, 2022-09-26 at 14:47 +0800, Chen-Yu Tsai wrote: > On Fri, Sep 23, 2022 at 7:47 PM Allen-KH Cheng > <allen-kh.cheng@mediatek.com> wrote: > > > > Add vcodec lat and core nodes for mt8192 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > Tested-by: Chen-Yu Tsai <wenst@chromium.org> > > > --- > > This patch is based on matthias.bgg/linux.git, v6.0-next/dts64 > > [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] > > --- > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 > > ++++++++++++++++++++++++ > > 1 file changed, 60 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index 6b20376191a7..aa6524948e7c 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -1449,6 +1449,66 @@ > > power-domains = <&spm > > MT8192_POWER_DOMAIN_ISP2>; > > }; > > > > + vcodec_dec: vcodec-dec@16000000 { > > The device node name should be generic, so maybe "video-codec@"? > > > + compatible = "mediatek,mt8192-vcodec-dec"; > > + reg = <0 0x16000000 0 0x1000>; > > + mediatek,scp = <&scp>; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 > > 0xfff00000>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges = <0 0 0 0x16000000 0 0x26000>; > > + > > + vcodec_lat: vcodec-lat@10000 { > > Same here. > > > + compatible = "mediatek,mtk-vcodec- > > lat"; > > + reg = <0x0 0x10000 0 0x800>; > > + interrupts = <GIC_SPI 426 > > IRQ_TYPE_LEVEL_HIGH 0>; > > + iommus = <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > > + <&iommu0 > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > > + clocks = <&topckgen > > CLK_TOP_VDEC_SEL>, > > + <&vdecsys_soc > > CLK_VDEC_SOC_VDEC>, > > + <&vdecsys_soc > > CLK_VDEC_SOC_LAT>, > > + <&vdecsys_soc > > CLK_VDEC_SOC_LARB1>, > > + <&topckgen > > CLK_TOP_MAINPLL_D4>; > > + clock-names = "sel", "soc-vdec", > > "soc-lat", "vdec", "top"; > > + assigned-clocks = <&topckgen > > CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen > > CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm > > MT8192_POWER_DOMAIN_VDEC>; > > + }; > > + > > + vcodec_core: vcodec-core@25000 { > > Same here. > > ChenYu
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 6b20376191a7..aa6524948e7c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1449,6 +1449,66 @@ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; }; + vcodec_dec: vcodec-dec@16000000 { + compatible = "mediatek,mt8192-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + mediatek,scp = <&scp>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0x16000000 0 0x26000>; + + vcodec_lat: vcodec-lat@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0x0 0x10000 0 0x800>; + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec-core@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1600d000 0 0x1000>;
Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- This patch is based on matthias.bgg/linux.git, v6.0-next/dts64 [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] --- --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+)