| Message ID | 20220926140932.820050-1-dinguyen@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PATCHv3,1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" | expand |
On 26/09/2022 16:09, Dinh Nguyen wrote: > +allOf: > + - $ref: "synopsys-dw-mshc-common.yaml#" > + > + - if: > + properties: > + compatible: > + contains: > + const: > + - altr,socfpga-dw-mshc > + then: > + required: > + - altr,sysmgr-syscon else: properties: altr,sysmgr-syscon: false and then you will probably see the warnings leading to error in syntax (const is not an array)... Best regards, Krzysztof
On 9/26/22 10:35, Krzysztof Kozlowski wrote: > On 26/09/2022 16:09, Dinh Nguyen wrote: >> +allOf: >> + - $ref: "synopsys-dw-mshc-common.yaml#" >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: >> + - altr,socfpga-dw-mshc >> + then: >> + required: >> + - altr,sysmgr-syscon > > else: > properties: > altr,sysmgr-syscon: false > and then you will probably see the warnings leading to error in syntax > (const is not an array)... > Hmm, okay. I ran dt_binding_check and did not see the warning. I'll check it again. Dinh
On Mon, 26 Sep 2022 09:09:30 -0500, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 28 +++++++++++++++++-- > 1 file changed, 25 insertions(+), 3 deletions(-) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb arch/arm/boot/dts/socfpga_vt.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'cd-gpios', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) arch/arm/boot/dts/socfpga_arria5_socdk.dtb arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb dwmmc0@ff704000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb arch/arm/boot/dts/socfpga_vt.dtb dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb dwmmc0@ff808000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'fifo-depth', 'resets' were unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb mmc@ff808000: Unevaluated properties are not allowed ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing', 'iommus' were unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb mmc@ff808000: Unevaluated properties are not allowed ('iommus' was unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dtb arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb mmcsd@40004000: $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$' arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: clock-names:0: 'biu' was expected arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: clock-names:1: 'ciu' was expected arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: Unevaluated properties are not allowed ('bus-width', 'clock-names', 'resets', 'vmmc-supply' were unexpected) arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb mmcsd@40004000: Unevaluated properties are not allowed ('clock-names', 'resets' were unexpected) arch/arm/boot/dts/lpc4337-ciaa.dtb arch/arm/boot/dts/lpc4350-hitex-eval.dtb
On Mon, Sep 26, 2022 at 11:49 AM Dinh Nguyen <dinguyen@kernel.org> wrote: > > > > On 9/26/22 10:35, Krzysztof Kozlowski wrote: > > On 26/09/2022 16:09, Dinh Nguyen wrote: > >> +allOf: > >> + - $ref: "synopsys-dw-mshc-common.yaml#" > >> + > >> + - if: > >> + properties: > >> + compatible: > >> + contains: > >> + const: > >> + - altr,socfpga-dw-mshc > >> + then: > >> + required: > >> + - altr,sysmgr-syscon > > > > else: > > properties: > > altr,sysmgr-syscon: false > > and then you will probably see the warnings leading to error in syntax > > (const is not an array)... > > > > Hmm, okay. I ran dt_binding_check and did not see the warning. I'll > check it again. Indeed, it does not warn. An array is allowed here as you could have a constant array value. Expect a warning soon though, as I'm working on adding one. Rob
Hi Rob, On 9/27/22 09:39, Rob Herring wrote: > On Mon, 26 Sep 2022 09:09:30 -0500, Dinh Nguyen wrote: >> Document the optional "altr,sysmgr-syscon" binding that is used to >> access the System Manager register that controls the SDMMC clock >> phase. >> >> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: document >> that the "altr,sysmgr-syscon" binding is only applicable to >> "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC >> section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 28 >> +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 >> deletions(-) >> > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for > dtbs_check. This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/patch/ > > > dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match > '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb > arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb > arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb > arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb > arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb > arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb > arch/arm/boot/dts/socfpga_vt.dtb > > dwmmc0@ff704000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'cd-gpios', 'fifo-depth', > 'resets', 'vmmc-supply', 'vqmmc-supply' were unexpected) > arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_sodia.dtb > > dwmmc0@ff704000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets', > 'vmmc-supply', 'vqmmc-supply' were unexpected) > arch/arm/boot/dts/socfpga_arria5_socdk.dtb > arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dtb > arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dtb > arch/arm/boot/dts/socfpga_cyclone5_sockit.dtb > > dwmmc0@ff704000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were > unexpected) arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dtb > arch/arm/boot/dts/socfpga_cyclone5_socrates.dtb > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dtb > arch/arm/boot/dts/socfpga_vt.dtb > > dwmmc0@ff808000: $nodename:0: 'dwmmc0@ff808000' does not match > '^mmc(@.*)?$' arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb > > dwmmc0@ff808000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-mmc-highspeed', 'cap-sd-highspeed', 'fifo-depth', 'resets' were > unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb > > dwmmc0@ff808000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'broken-cd', 'bus-width', > 'cap-sd-highspeed', 'fifo-depth', 'resets' were unexpected) > arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb > > dwmmc0@ff808000: Unevaluated properties are not allowed > ('#address-cells', '#size-cells', 'fifo-depth', 'resets' were > unexpected) arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb > arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb > > mmc@ff808000: Unevaluated properties are not allowed > ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing', 'iommus' were > unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dtb > > mmc@ff808000: Unevaluated properties are not allowed ('iommus' was > unexpected) arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb > arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb > arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dtb > arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb > arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dtb > arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb > > mmcsd@40004000: $nodename:0: 'mmcsd@40004000' does not match > '^mmc(@.*)?$' arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: clock-names:0: 'biu' was expected > arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: clock-names:1: 'ciu' was expected > arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: Unevaluated properties are not allowed ('bus-width', > 'clock-names', 'resets', 'vmmc-supply' were unexpected) > arch/arm/boot/dts/lpc4357-ea4357-devkit.dtb > arch/arm/boot/dts/lpc4357-myd-lpc4357.dtb > > mmcsd@40004000: Unevaluated properties are not allowed > ('clock-names', 'resets' were unexpected) > arch/arm/boot/dts/lpc4337-ciaa.dtb > arch/arm/boot/dts/lpc4350-hitex-eval.dtb > Hmm, I see these warnings on the standard v6.0-rc1 and linux-next(next-20220923), but with this patch applied I don't see any warnings regarding MMC. DTC arch/arm/boot/dts/socfpga_arria5_socdk.dtb DTC arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb DTC arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb DTC arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb CHECK arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb CHECK arch/arm/boot/dts/socfpga_arria5_socdk.dtb CHECK arch/arm/boot/dts/socfpga_arria10_chameleonv3.dtb CHECK arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: pmu@ff111000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /home/dinguyen/linux_dev/linux/Documentation/devicetree/bindings/arm/pmu.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: amba: {'compatible': ['simple-bus'], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'pdma@ffda1000': {'compatible': ['arm,pl330', 'arm,primecell'], 'reg': [[4292481024, 4096]], 'interrupts': [[0, 83, 4], [0, 84, 4], [0, 85, 4], [0, 86, 4], [0, 87, 4], [0, 88, 4], [0, 89, 4], [0, 90, 4], [0, 91, 4]], '#dma-cells': [[1]], 'clocks': [[5]], 'clock-names': ['apb_pclk'], 'resets': [[6, 48], [6, 53]], 'reset-names': ['dma', 'dma-ocp'], 'phandle': [[34]]}} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: base_fpga_region: {'#address-cells': [[1]], '#size-cells': [[1]], 'compatible': ['fpga-region'], 'fpga-mgr': [[7]]} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: stmmac-axi-config: {'snps,wr_osr_lmt': [[15]], 'snps,rd_osr_lmt': [[15]], 'snps,blen': [[0, 0, 0, 0, 16, 0, 0]], 'phandle': [[30]]} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: eccmgr: {'compatible': ['altr,socfpga-a10-ecc-manager'], 'altr,sysmgr-syscon': [[28]], '#address-cells': [[1]], '#size-cells': [[1]], 'interrupts': [[0, 2, 4], [0, 0, 4]], 'interrupt-controller': True, '#interrupt-cells': [[2]], 'ranges': True, 'sdramedac': {'compatible': ['altr,sdram-edac-a10'], 'altr,sdr-syscon': [[39]], 'interrupts': [[17, 4], [49, 4]]}, 'l2-ecc@ffd06010': {'compatible': ['altr,socfpga-a10-l2-ecc'], 'reg': [[4291846160, 4]], 'interrupts': [[0, 4], [32, 4]]}, 'ocram-ecc@ff8c3000': {'compatible': ['altr,socfpga-a10-ocram-ecc'], 'reg': [[4287377408, 1024]], 'interrupts': [[1, 4], [33, 4]]}, 'emac0-rx-ecc@ff8c0800': {'compatible': ['altr,socfpga-eth-mac-ecc'], 'reg': [[4287367168, 1024]], 'altr,ecc-parent': [[40]], 'interrupts': [[4, 4], [36, 4]]}, 'emac0-tx-ecc@ff8c0c00': {'compatible': ['altr,socfpga-eth-mac-ecc'], 'reg': [[4287368192, 1024]], 'altr,ecc-parent': [[40]], 'interrupts': [[5, 4], [37, 4]]}, 'sdmmca-ecc@ff8c2c00': {'compatible': ['altr,socfpga-sdmmc-ecc'], 'reg': [[4287376384, 1024]], 'altr,ecc-parent': [[41]], 'interrupts': [[15, 4], [47, 4], [16, 4], [48, 4]]}, 'dma-ecc@ff8c8000': {'compatible': ['altr,socfpga-dma-ecc'], 'reg': [[4287397888, 1024]], 'altr,ecc-parent': [[34]], 'interrupts': [[10, 4], [42, 4]]}, 'usb0-ecc@ff8c8800': {'compatible': ['altr,socfpga-usb-ecc'], 'reg': [[4287399936, 1024]], 'altr,ecc-parent': [[42]], 'interrupts': [[2, 4], [34, 4]]}} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: soc: usbphy: {'#phy-cells': [[0]], 'compatible': ['usb-nop-xceiv'], 'status': ['okay'], 'phandle': [[47]]} should not be valid under {'type': 'object'} From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /home/dinguyen/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml /home/dinguyen/linux_dev/linux/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb: pdma@ffda1000: $nodename:0: 'pdma@ffda1000' does not match '^dma-controller(@.*)?$' From schema: /home/dinguyen/linux_dev/linux/Documentation/devicetree/bindings/dma/arm,pl330.yaml Dinh
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..fc7ea20f1d8c 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -38,6 +35,31 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + description: + Contains the phandle to System Manager block that contains + the SDMMC clock-phase control register. The first value is the pointer + to the sysmgr and the 2nd value is the register offset for the SDMMC + clock phase register. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + + - if: + properties: + compatible: + contains: + const: + - altr,socfpga-dw-mshc + then: + required: + - altr,sysmgr-syscon + required: - compatible - reg
Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-)