diff mbox series

[v2] dmaengine: ti: k3-udma: Respond TX done if DMA_PREP_INTERRUPT is not requested

Message ID 20220914110049.5842-1-vaishnav.a@ti.com (mailing list archive)
State Accepted
Commit e8e2f92b1553b977aef8bb4fa4e4c5b69c8d9d54
Headers show
Series [v2] dmaengine: ti: k3-udma: Respond TX done if DMA_PREP_INTERRUPT is not requested | expand

Commit Message

Vaishnav Achath Sept. 14, 2022, 11 a.m. UTC 
If the DMA consumer driver does not expect the callback for TX done, then
we need not perform the channel RT byte counter calculations and estimate
the completion but return complete on first attempt itself.This assumes
that the consumer who did not request DMA_PREP_INTERRUPT has its own
mechanism for understanding TX completion, example: MCSPI EOW interrupt
can be used as TX completion signal for a SPI transaction.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
---

V1->V2:
	* Add comment to explain the expectations from the consumer
	when DMA_PREP_INTERRUPT is not requested.
	* v1 was sent as series:
	https://lore.kernel.org/lkml/20220822091531.27827-2-vaishnav.a@ti.com/

 drivers/dma/ti/k3-udma.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

Comments

Vinod Koul Sept. 29, 2022, 5:05 p.m. UTC | #1 
On 14-09-22, 16:30, Vaishnav Achath wrote:
> If the DMA consumer driver does not expect the callback for TX done, then
> we need not perform the channel RT byte counter calculations and estimate
> the completion but return complete on first attempt itself.This assumes
> that the consumer who did not request DMA_PREP_INTERRUPT has its own
> mechanism for understanding TX completion, example: MCSPI EOW interrupt
> can be used as TX completion signal for a SPI transaction.

Applied, thanks
diff mbox series

Patch

diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 39b330ada200..fbb80a6e59b2 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -263,6 +263,7 @@  struct udma_chan_config {
 	enum udma_tp_level channel_tpl; /* Channel Throughput Level */
 
 	u32 tr_trigger_type;
+	unsigned long tx_flags;
 
 	/* PKDMA mapped channel */
 	int mapped_channel_id;
@@ -1055,9 +1056,14 @@  static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d)
 {
 	u32 peer_bcnt, bcnt;
 
-	/* Only TX towards PDMA is affected */
+	/*
+	 * Only TX towards PDMA is affected.
+	 * If DMA_PREP_INTERRUPT is not set by consumer then skip the transfer
+	 * completion calculation, consumer must ensure that there is no stale
+	 * data in DMA fabric in this case.
+	 */
 	if (uc->config.ep_type == PSIL_EP_NATIVE ||
-	    uc->config.dir != DMA_MEM_TO_DEV)
+	    uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT))
 		return true;
 
 	peer_bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
@@ -3418,6 +3424,8 @@  udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 	if (!burst)
 		burst = 1;
 
+	uc->config.tx_flags = tx_flags;
+
 	if (uc->config.pkt_mode)
 		d = udma_prep_slave_sg_pkt(uc, sgl, sglen, dir, tx_flags,
 					   context);