[RESEND,v3,2/3] clk: imx: imx8mp: add shared clk gate for usb suspend clk

Commit Message

Jun Li Sept. 23, 2022, 10:45 a.m. UTC

32K usb suspend clock gate is shared with usb_root_clk.

Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver")
Cc: [e-mail] # v5.19+
Tested-by: Alexander Stein <[e-mail]>
Signed-off-by: Li Jun <[e-mail]>
---
 drivers/clk/imx/clk-imx8mp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Stephen Boyd Sept. 30, 2022, 12:53 a.m. UTC | #1

Quoting Li Jun (2022-09-23 03:45:04)
> 32K usb suspend clock gate is shared with usb_root_clk.
> 
> Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver")
> Cc: [e-mail] # v5.19+

Why is stable Cced? The commit text doesn't tell me what sort of
regression is being fixed. Please help!

Jun Li Sept. 30, 2022, 2:14 a.m. UTC | #2

Hi Stephen,

> -----Original Message-----
> From: Stephen Boyd <[e-mail]>
> Sent: Friday, September 30, 2022 8:54 AM
> To: Jun Li <[e-mail]>; [e-mail]
> Cc: [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; dl-linux-imx <[e-mail]>;
> [e-mail]; [e-mail]; Peng Fan
> <[e-mail]>; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]
> Subject: Re: [PATCH RESEND v3 2/3] clk: imx: imx8mp: add shared clk gate
> for usb suspend clk
> 
> Quoting Li Jun (2022-09-23 03:45:04)
> > 32K usb suspend clock gate is shared with usb_root_clk.
> >
> > Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock
> > driver")
> > Cc: [e-mail] # v5.19+
> 
> Why is stable Cced? The commit text doesn't tell me what sort of regression
> is being fixed. Please help!

Sorry, I missed this again, Rob commented on this.
I will resend with commit text improved to explain this.

Thanks
Li Jun

Patch

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index e89db568f5a8..5b66514bdd0c 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -17,6 +17,7 @@ 
 
 static u32 share_count_nand;
 static u32 share_count_media;
+static u32 share_count_usb;
 
 static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
@@ -673,7 +674,8 @@  static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
 	hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
 	hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
-	hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0);
+	hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb);
+	hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb);
 	hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
 	hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
 	hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);