diff mbox series

[v8,1/4] mailbox: mtk-cmdq: add gce software ddr enable private data

Message ID 20220930160638.7588-2-yongqiang.niu@mediatek.com (mailing list archive)
State New, archived
Headers show
Series mailbox: mtk-cmdq: add MT8186 support | expand

Commit Message

Yongqiang Niu Sept. 30, 2022, 4:06 p.m. UTC 
if gce work control by software, we need set software enable
for MT8186 Soc

there is a handshake flow between gce and ddr hardware,
if not set ddr enable flag of gce, ddr will fall into idle
mode, then gce instructions will not process done.
we need set this flag of gce to tell ddr when gce is idle or busy
controlled by software flow.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

CK Hu (胡俊光) Oct. 3, 2022, 4 a.m. UTC | #1 
Hi, Yongqiang:

On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> if gce work control by software, we need set software enable
> for MT8186 Soc
> 
> there is a handshake flow between gce and ddr hardware,
> if not set ddr enable flag of gce, ddr will fall into idle
> mode, then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9465f9081515..88db6b4642db 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -38,6 +38,8 @@
>  #define CMDQ_THR_PRIORITY		0x40
>  
>  #define GCE_GCTL_VALUE			0x48
> +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> +#define GCE_DDR_EN				GENMASK(18, 16)
>  
>  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
>  #define CMDQ_THR_ENABLED		0x1
> @@ -80,6 +82,7 @@ struct cmdq {
>  	bool			suspended;
>  	u8			shift_pa;
>  	bool			control_by_sw;
> +	bool			sw_ddr_en;
>  	u32			gce_num;
>  };
>  
> @@ -87,6 +90,7 @@ struct gce_plat {
>  	u32 thread_nr;
>  	u8 shift;
>  	bool control_by_sw;
> +	bool sw_ddr_en;
>  	u32 gce_num;
>  };
>  
> @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
>  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>  	if (cmdq->control_by_sw)
>  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> +
> +	if (cmdq->sw_ddr_en)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> GCE_GCTL_VALUE);

I think 0x48[18:16] and 0x48[2:0] control different things and fix
different problem. So for this patch, you should just control
0x48[18:16] and the code would be:

if (cmdq->sw_ddr_en) {
	reg = readl(cmdq->base + GCE_GCTL_VALUE);
	reg |= GCE_DDR_EN;
	writel(reg, cmdq->base + GCE_GCTL_VALUE);
}

Regards,
CK

> +
>  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> CMDQ_THR_SLOT_CYCLES);
>  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
>  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> *pdev)
>  	cmdq->thread_nr = plat_data->thread_nr;
>  	cmdq->shift_pa = plat_data->shift;
>  	cmdq->control_by_sw = plat_data->control_by_sw;
> +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
>  	cmdq->gce_num = plat_data->gce_num;
>  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
>  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> IRQF_SHARED,
Yongqiang Niu Oct. 4, 2022, 9:35 a.m. UTC | #2 
On Mon, 2022-10-03 at 12:00 +0800, CK Hu (胡俊光) wrote:
> Hi, Yongqiang:
> 
> On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > if gce work control by software, we need set software enable
> > for MT8186 Soc
> > 
> > there is a handshake flow between gce and ddr hardware,
> > if not set ddr enable flag of gce, ddr will fall into idle
> > mode, then gce instructions will not process done.
> > we need set this flag of gce to tell ddr when gce is idle or busy
> > controlled by software flow.
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 9465f9081515..88db6b4642db 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -38,6 +38,8 @@
> >  #define CMDQ_THR_PRIORITY		0x40
> >  
> >  #define GCE_GCTL_VALUE			0x48
> > +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> > +#define GCE_DDR_EN				GENMASK(18, 16)
> >  
> >  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
> >  #define CMDQ_THR_ENABLED		0x1
> > @@ -80,6 +82,7 @@ struct cmdq {
> >  	bool			suspended;
> >  	u8			shift_pa;
> >  	bool			control_by_sw;
> > +	bool			sw_ddr_en;
> >  	u32			gce_num;
> >  };
> >  
> > @@ -87,6 +90,7 @@ struct gce_plat {
> >  	u32 thread_nr;
> >  	u8 shift;
> >  	bool control_by_sw;
> > +	bool sw_ddr_en;
> >  	u32 gce_num;
> >  };
> >  
> > @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
> >  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> >  	if (cmdq->control_by_sw)
> >  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> > +
> > +	if (cmdq->sw_ddr_en)
> > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > GCE_GCTL_VALUE);
> 
> I think 0x48[18:16]0x48[2:0] and 0x48[2:0] control different things
> and fix
> different problem. So for this patch, you should just control
> 0x48[18:16] and the code would be:
> 
> if (cmdq->sw_ddr_en) {
> 	reg = readl(cmdq->base + GCE_GCTL_VALUE);
> 	reg |= GCE_DDR_EN;
> 	writel(reg, cmdq->base + GCE_GCTL_VALUE);
> }
> 
> Regards,
> CK

0x48[2:0] means control by software
0x48[18:16] means ddr enable 
0x48[2:0] is pre-condition of 0x48[18:16].
if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
time.


> 
> > +
> >  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> > CMDQ_THR_SLOT_CYCLES);
> >  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> >  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> > @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> > *pdev)
> >  	cmdq->thread_nr = plat_data->thread_nr;
> >  	cmdq->shift_pa = plat_data->shift;
> >  	cmdq->control_by_sw = plat_data->control_by_sw;
> > +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
> >  	cmdq->gce_num = plat_data->gce_num;
> >  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> >  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> > IRQF_SHARED,
CK Hu (胡俊光) Oct. 4, 2022, 10:08 a.m. UTC | #3 
Hi, Yongqiang:

On Tue, 2022-10-04 at 17:35 +0800, yongqiang.niu wrote:
> On Mon, 2022-10-03 at 12:00 +0800, CK Hu (胡俊光) wrote:
> > Hi, Yongqiang:
> > 
> > On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > > if gce work control by software, we need set software enable
> > > for MT8186 Soc
> > > 
> > > there is a handshake flow between gce and ddr hardware,
> > > if not set ddr enable flag of gce, ddr will fall into idle
> > > mode, then gce instructions will not process done.
> > > we need set this flag of gce to tell ddr when gce is idle or busy
> > > controlled by software flow.
> > > 
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > >  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > index 9465f9081515..88db6b4642db 100644
> > > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > @@ -38,6 +38,8 @@
> > >  #define CMDQ_THR_PRIORITY		0x40
> > >  
> > >  #define GCE_GCTL_VALUE			0x48
> > > +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> > > +#define GCE_DDR_EN				GENMASK(18, 16)
> > >  
> > >  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
> > >  #define CMDQ_THR_ENABLED		0x1
> > > @@ -80,6 +82,7 @@ struct cmdq {
> > >  	bool			suspended;
> > >  	u8			shift_pa;
> > >  	bool			control_by_sw;
> > > +	bool			sw_ddr_en;
> > >  	u32			gce_num;
> > >  };
> > >  
> > > @@ -87,6 +90,7 @@ struct gce_plat {
> > >  	u32 thread_nr;
> > >  	u8 shift;
> > >  	bool control_by_sw;
> > > +	bool sw_ddr_en;
> > >  	u32 gce_num;
> > >  };
> > >  
> > > @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
> > >  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> > >  	if (cmdq->control_by_sw)
> > >  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> > > +
> > > +	if (cmdq->sw_ddr_en)
> > > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > > GCE_GCTL_VALUE);
> > 
> > I think 0x48[18:16]0x48[2:0] and 0x48[2:0] control different things
> > and fix
> > different problem. So for this patch, you should just control
> > 0x48[18:16] and the code would be:
> > 
> > if (cmdq->sw_ddr_en) {
> > 	reg = readl(cmdq->base + GCE_GCTL_VALUE);
> > 	reg |= GCE_DDR_EN;
> > 	writel(reg, cmdq->base + GCE_GCTL_VALUE);
> > }
> > 
> > Regards,
> > CK
> 
> 0x48[2:0] means control by software
> 0x48[18:16] means ddr enable 
> 0x48[2:0] is pre-condition of 0x48[18:16].
> if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
> time.

OK, add comment for this.

> 
> 
> > 
> > > +
> > >  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> > > CMDQ_THR_SLOT_CYCLES);
> > >  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> > >  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> > > @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> > > *pdev)
> > >  	cmdq->thread_nr = plat_data->thread_nr;
> > >  	cmdq->shift_pa = plat_data->shift;
> > >  	cmdq->control_by_sw = plat_data->control_by_sw;
> > > +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
> > >  	cmdq->gce_num = plat_data->gce_num;
> > >  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> > >  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> > > IRQF_SHARED,
> 
>
diff mbox series

Patch

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9465f9081515..88db6b4642db 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -38,6 +38,8 @@ 
 #define CMDQ_THR_PRIORITY		0x40
 
 #define GCE_GCTL_VALUE			0x48
+#define GCE_CTRL_BY_SW				GENMASK(2, 0)
+#define GCE_DDR_EN				GENMASK(18, 16)
 
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
@@ -80,6 +82,7 @@  struct cmdq {
 	bool			suspended;
 	u8			shift_pa;
 	bool			control_by_sw;
+	bool			sw_ddr_en;
 	u32			gce_num;
 };
 
@@ -87,6 +90,7 @@  struct gce_plat {
 	u32 thread_nr;
 	u8 shift;
 	bool control_by_sw;
+	bool sw_ddr_en;
 	u32 gce_num;
 };
 
@@ -130,6 +134,10 @@  static void cmdq_init(struct cmdq *cmdq)
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
 		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
+
+	if (cmdq->sw_ddr_en)
+		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
@@ -543,6 +551,7 @@  static int cmdq_probe(struct platform_device *pdev)
 	cmdq->thread_nr = plat_data->thread_nr;
 	cmdq->shift_pa = plat_data->shift;
 	cmdq->control_by_sw = plat_data->control_by_sw;
+	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
 	cmdq->gce_num = plat_data->gce_num;
 	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,