| Message ID | 20220928155511.2379663-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4.1] drm/i915/mtl: Define engine context layouts | expand |
On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote: >From: Matt Roper <matthew.d.roper@intel.com> > >The part of the media and blitter engine contexts that we care about for >setting up an initial state on MTL are nearly similar to DG2 (and PVC). >The difference being PRT_BB_STATE being replaced with NOP. > >For render/compute engines, the part of the context images are nearly >the same, although the layout had a very slight change --- one POSH >register was removed and the placement of some LRI/noops adjusted >slightly to compensate. > >v2: > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala) > - Add missing nop in xcs offsets(Bala) >v3: > - Fix the spacing for nop in xcs offset(MattR) >v4: > - Fix rcs register offset(MattR) >v4.1: > - Fix commit message(Lucas) > >Bspec: 46261, 46260, 45585 >Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> >Cc: Licas De Marchi <lucas.demarchi@intel.com> >Signed-off-by: Matt Roper <matthew.d.roper@intel.com> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi
> -----Original Message----- > From: De Marchi, Lucas <lucas.demarchi@intel.com> > Sent: Thursday, September 29, 2022 5:11 PM > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org > Subject: Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts > > On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote: > >From: Matt Roper <matthew.d.roper@intel.com> > > > >The part of the media and blitter engine contexts that we care about for > >setting up an initial state on MTL are nearly similar to DG2 (and PVC). > >The difference being PRT_BB_STATE being replaced with NOP. > > > >For render/compute engines, the part of the context images are nearly > >the same, although the layout had a very slight change --- one POSH > >register was removed and the placement of some LRI/noops adjusted > >slightly to compensate. > > > >v2: > > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala) > > - Add missing nop in xcs offsets(Bala) > >v3: > > - Fix the spacing for nop in xcs offset(MattR) > >v4: > > - Fix rcs register offset(MattR) > >v4.1: > > - Fix commit message(Lucas) > > > >Bspec: 46261, 46260, 45585 > >Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> > >Cc: Licas De Marchi <lucas.demarchi@intel.com> > >Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Pushed the patch, Thanks for the review. -Radhakrishna Sripada > > Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 82d899f170fb..e84ef3859934 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = { END }; +static const u8 mtl_xcs_offsets[] = { + NOP(1), + LRI(13, POSTED), + REG16(0x244), + REG(0x034), + REG(0x030), + REG(0x038), + REG(0x03c), + REG(0x168), + REG(0x140), + REG(0x110), + REG(0x1c0), + REG(0x1c4), + REG(0x1c8), + REG(0x180), + REG16(0x2b4), + NOP(4), + + NOP(1), + LRI(9, POSTED), + REG16(0x3a8), + REG16(0x28c), + REG16(0x288), + REG16(0x284), + REG16(0x280), + REG16(0x27c), + REG16(0x278), + REG16(0x274), + REG16(0x270), + + END +}; + static const u8 gen8_rcs_offsets[] = { NOP(1), LRI(14, POSTED), @@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = { END }; +static const u8 mtl_rcs_offsets[] = { + NOP(1), + LRI(15, POSTED), + REG16(0x244), + REG(0x034), + REG(0x030), + REG(0x038), + REG(0x03c), + REG(0x168), + REG(0x140), + REG(0x110), + REG(0x1c0), + REG(0x1c4), + REG(0x1c8), + REG(0x180), + REG16(0x2b4), + REG(0x120), + REG(0x124), + + NOP(1), + LRI(9, POSTED), + REG16(0x3a8), + REG16(0x28c), + REG16(0x288), + REG16(0x284), + REG16(0x280), + REG16(0x27c), + REG16(0x278), + REG16(0x274), + REG16(0x270), + + NOP(2), + LRI(2, POSTED), + REG16(0x5a8), + REG16(0x5ac), + + NOP(6), + LRI(1, 0), + REG(0x0c8), + + END +}; + #undef END #undef REG16 #undef REG @@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) !intel_engine_has_relative_mmio(engine)); if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) { - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) + return mtl_rcs_offsets; + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) return dg2_rcs_offsets; else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) return xehp_rcs_offsets; @@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) else return gen8_rcs_offsets; } else { - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) + return mtl_xcs_offsets; + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) return dg2_xcs_offsets; else if (GRAPHICS_VER(engine->i915) >= 12) return gen12_xcs_offsets;