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[v2] net: mv643xx_eth: support MII/GMII/RGMII modes

Message ID 20220930203926.958776-1-mmyangfl@gmail.com (mailing list archive)
State Superseded
Delegated to: Netdev Maintainers
Headers show
Series [v2] net: mv643xx_eth: support MII/GMII/RGMII modes | expand

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netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 6 this patch: 6
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Commit Message

David Yang Sept. 30, 2022, 8:39 p.m. UTC 
Support mode switch properly, which is not available before.

If SoC has two Ethernet controllers, by setting both of them into MII
mode, the first controller enters GMII mode, while the second
controller is effectively disabled. This requires configuring (and
maybe enabling) the second controller in the device tree, even though
it cannot be used.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
v2: clarify modes work on controllers, read default value from PSC1
 drivers/net/ethernet/marvell/mv643xx_eth.c | 36 ++++++++++++++++++++--
 1 file changed, 33 insertions(+), 3 deletions(-)

Comments

Paolo Abeni Oct. 4, 2022, 8:52 a.m. UTC | #1 
Hello,

On Sat, 2022-10-01 at 04:39 +0800, David Yang wrote:
> Support mode switch properly, which is not available before.
> 
> If SoC has two Ethernet controllers, by setting both of them into MII
> mode, the first controller enters GMII mode, while the second
> controller is effectively disabled. This requires configuring (and
> maybe enabling) the second controller in the device tree, even though
> it cannot be used.
> 
> Signed-off-by: David Yang <mmyangfl@gmail.com>

It looks like that despite the subj change, this is superseded by:

https://patchwork.kernel.org/project/netdevbpf/patch/20221001174524.2007912-1-mmyangfl@gmail.com/

I'm updating the PW accordingly. Please let me know if you intended
otherwise.

Thanks,

Paolo
diff mbox series

Patch

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index b6be0552a..ddaccc979 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -108,6 +108,7 @@  static char mv643xx_eth_driver_version[] = "1.4";
 #define TXQ_COMMAND			0x0048
 #define TXQ_FIX_PRIO_CONF		0x004c
 #define PORT_SERIAL_CONTROL1		0x004c
+#define  RGMII_EN			0x00000008
 #define  CLK125_BYPASS_EN		0x00000010
 #define TX_BW_RATE			0x0050
 #define TX_BW_MTU			0x0058
@@ -1215,6 +1216,7 @@  static void mv643xx_eth_adjust_link(struct net_device *dev)
 	             DISABLE_AUTO_NEG_SPEED_GMII |
 		     DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
 		     DISABLE_AUTO_NEG_FOR_DUPLEX;
+	u32 psc1r = rdlp(mp, PORT_SERIAL_CONTROL1);
 
 	if (dev->phydev->autoneg == AUTONEG_ENABLE) {
 		/* enable auto negotiation */
@@ -1245,6 +1247,30 @@  static void mv643xx_eth_adjust_link(struct net_device *dev)
 
 out_write:
 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
+
+	/* If two Ethernet controllers present in the SoC, and both of them have
+	 * RGMII_EN disabled, the first controller will be in GMII mode and the
+	 * second one is effectively disabled, instead of two MII interfaces.
+	 *
+	 * To enable GMII in the first controller, the second one must also be
+	 * configured (and may be enabled) with RGMII_EN disabled too, even
+	 * though it cannot be used at all.
+	 */
+	switch (dev->phydev->interface) {
+	case PHY_INTERFACE_MODE_MII:
+	case PHY_INTERFACE_MODE_GMII:
+		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r & ~RGMII_EN);
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		wrlp(mp, PORT_SERIAL_CONTROL1, psc1r | RGMII_EN);
+		break;
+	default:
+		/* Unknown; don't touch */
+		break;
+	}
 }
 
 /* statistics ***************************************************************/
@@ -2975,11 +3001,15 @@  static int get_phy_mode(struct mv643xx_eth_private *mp)
 	if (dev->of_node)
 		err = of_get_phy_mode(dev->of_node, &iface);
 
-	/* Historical default if unspecified. We could also read/write
-	 * the interface state in the PSC1
+	/* Read the interface state in the PSC1.
+	 *
+	 * Modes of two devices may interact; see comments in
+	 * mv643xx_eth_adjust_link. Currently there is no way to detect another
+	 * device within this scope; blindly set MII here.
 	 */
 	if (!dev->of_node || err)
-		iface = PHY_INTERFACE_MODE_GMII;
+		iface = rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN ?
+			PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
 	return iface;
 }