| Message ID | 20221009230044.10961-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: rzg2l/rzg2lc/rzg2ul/rzv2l: Drop WDT2 | expand |
On Mon, Oct 10, 2022 at 12:00:43AM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if > used from CA55 CPU would result in an unexpected behaviour. Hence drop > WDT2 node from RZ/V2L SoC DTSI. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Hi Prabhakar, On Mon, Oct 10, 2022 at 1:01 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if > used from CA55 CPU would result in an unexpected behaviour. Hence drop > WDT2 node from RZ/V2L SoC DTSI. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi > @@ -1000,21 +1000,6 @@ wdt1: watchdog@12800c00 { > status = "disabled"; > }; > > - wdt2: watchdog@12800400 { > - compatible = "renesas,r9a07g054-wdt", > - "renesas,rzg2l-wdt"; > - reg = <0 0x12800400 0 0x400>; > - clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, > - <&cpg CPG_MOD R9A07G054_WDT2_CLK>; > - clock-names = "pclk", "oscclk"; > - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "wdt", "perrout"; > - resets = <&cpg R9A07G054_WDT2_PRESETN>; > - power-domains = <&cpg>; > - status = "disabled"; > - }; > - > ostm0: timer@12801000 { > compatible = "renesas,r9a07g054-ostm", > "renesas,ostm"; As this is hardware description, and the node is disabled by default, we could keep it. However, as it is to be used by the CM33, its interrupts property should point to the CM33 NVIC instead of the CA55 GIC. So let's drop it for now... Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.2. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 358d4c34465f..7c7bbe377699 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1000,21 +1000,6 @@ wdt1: watchdog@12800c00 { status = "disabled"; }; - wdt2: watchdog@12800400 { - compatible = "renesas,r9a07g054-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800400 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, - <&cpg CPG_MOD R9A07G054_WDT2_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G054_WDT2_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - ostm0: timer@12801000 { compatible = "renesas,r9a07g054-ostm", "renesas,ostm";