mbox series

[v12,0/4] Add the iMX8MP PCIe support

Message ID 1665387971-17114-1-git-send-email-hongxing.zhu@nxp.com
Headers show
Series Add the iMX8MP PCIe support | expand

Message

Hongxing Zhu Oct. 10, 2022, 7:46 a.m. UTC 
Based on the 6.0-rc1 of the pci/next branch. 
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.

- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
  Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
  And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
  driver.

Main changes v11-->v12:
 - In the local down kernel(6.0-rc7 plus local codes) PM tests, i.MX8MP
   PCIe encounters link failure during resume.
   To resolve this failure, the resets of i.MX8MP PCIe PHY should be always
   kept 1b'1. Merge the fix into v12 patches here.

Main changes v10-->v11:
Refer to Ahmad's comments do the following changes;
 - Correct the spell mistake and refine the commit log.
 - Make codes indent by the member name
 - Use the dev_err_probe replace the dev_err.

Main changes v9-->v10:
- Refer to Vinod's review comments, drop the array, and use the static data
  structure directly in the drvdata definition.

Main changes v8-->v9:
- Split the PHY driver changes into three patches.
  - To keep the format consistent, re-define the PHY_CMN_REG75, and remove
    two useless BIT definitions.
  - Refine the i.MX8MM PCIe PHY driver, let it more reviewable, flexible,
    and easy to expand.
  - Add the i.MX8MP PCIe PHY support.
- Only PHY related patches in v9, Since the others patches had been merged
  by Phillipp/Shawn/Lorenzo.

Main changes v7-->v8:
- Add the Reviewed-by tag, no other changes.
  Only two patches in v8, Since the others patches had been merged by
  Phillipp/Shawn/Lorenzo.

<snipped.>

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16 ++++++++--
drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 142 ++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------
2 files changed, 106 insertions(+), 52 deletions(-)

[PATCH v12 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding
[PATCH v12 2/4] phy: freescale: imx8m-pcie: Refine register
[PATCH v12 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY
[PATCH v12 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY

Comments

Tim Harvey Oct. 12, 2022, 6:31 p.m. UTC | #1 
On Mon, Oct 10, 2022 at 1:07 AM Richard Zhu <hongxing.zhu@nxp.com> wrote:
>
> Based on the 6.0-rc1 of the pci/next branch.
> This series adds the i.MX8MP PCIe support and tested on i.MX8MP
> EVK board when one PCIe NVME device is used.
>

Richard,

This no longer applies to pci/next (pci-v6.1-changes) and needs to be
rebased. It does apply on top of 6.0-rc1 but then the patches to
pci-imx6.c and imx8mp.dtsi are missing so I'm not sure where to try to
base this off of.

Do you have a repo for testing and have you been able to test a Gen3
link with A1 silicon yet?

Best Regards,

Tim
Hongxing Zhu Oct. 13, 2022, 12:45 a.m. UTC | #2 
> -----Original Message-----
> From: Tim Harvey <tharvey@gateworks.com>
> Sent: 2022年10月13日 2:31
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: vkoul@kernel.org; a.fatoum@pengutronix.de; p.zabel@pengutronix.de;
> l.stach@pengutronix.de; bhelgaas@google.com; lorenzo.pieralisi@arm.com;
> robh@kernel.org; shawnguo@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de; richard.leitner@linux.dev; linux-phy@lists.infradead.org;
> devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v12 0/4] Add the iMX8MP PCIe support
> 
> On Mon, Oct 10, 2022 at 1:07 AM Richard Zhu <hongxing.zhu@nxp.com>
> wrote:
> >
> > Based on the 6.0-rc1 of the pci/next branch.
> > This series adds the i.MX8MP PCIe support and tested on i.MX8MP EVK
> > board when one PCIe NVME device is used.
> >
> 
> Richard,
> 
> This no longer applies to pci/next (pci-v6.1-changes) and needs to be rebased.
> It does apply on top of 6.0-rc1 but then the patches to pci-imx6.c and
> imx8mp.dtsi are missing so I'm not sure where to try to base this off of.
> 
> Do you have a repo for testing and have you been able to test a Gen3 link with
> A1 silicon yet?
> 
Hi Tim:
Thanks for your concerns.
Yes, I used one NVME device to test the Gen3 link on i.MX8MP(A1) EVK board.
Okay, I would resend this version after rebase to pci-v6.1-changes.

Best Regards
Richard Zhu

> Best Regards,
> 
> Tim