Message ID | 20221020160022.1823365-1-imre.deak@intel.com (mailing list archive) |
---|---|
Headers | show |
Series | drm/i915/tgl+: Fix race conditions during DKL PHY accesses | expand |
On Thu, 20 Oct 2022, Imre Deak <imre.deak@intel.com> wrote: > This is v2 of [1] addressing the review comments from Jani. Did not do detailed review, Acked-by: Jani Nikula <jani.nikula@intel.com> > > [1] https://lore.kernel.org/intel-gfx/Y1BaRfTAH%2Fl+XLqc@ideak-desk.fi.intel.com/T/#t > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Imre Deak (4): > drm/i915/tgl+: Add locking around DKL PHY register accesses > drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h > drm/i915/tgl+: Move DKL PHY register definitions to > intel_dkl_phy_regs.h > drm/i915/tgl+: Sanitize DKL PHY register definitions > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/intel_ddi.c | 71 +++--- > .../gpu/drm/i915/display/intel_display_core.h | 4 + > .../i915/display/intel_display_power_well.c | 8 +- > drivers/gpu/drm/i915/display/intel_dkl_phy.c | 101 +++++++++ > drivers/gpu/drm/i915/display/intel_dkl_phy.h | 20 ++ > .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 202 ++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 62 +++--- > ...ntel_tc_phy_regs.h => intel_mg_phy_regs.h} | 6 +- > drivers/gpu/drm/i915/display/intel_tc.c | 3 +- > drivers/gpu/drm/i915/i915_driver.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 176 --------------- > 12 files changed, 397 insertions(+), 258 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c > create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h > create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h > rename drivers/gpu/drm/i915/display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h} (99%)