diff mbox series

[net-next,v5,5/5] ARM: dts: qcom: ipq4019: Add description for the IPQESS Ethernet controller

Message ID 20221021124556.100445-6-maxime.chevallier@bootlin.com (mailing list archive)
State Superseded
Delegated to: Netdev Maintainers
Headers show
Series net: ipqess: introduce Qualcomm IPQESS driver | expand

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netdev/cc_maintainers warning 5 maintainers not CCed: krzysztof.kozlowski+dt@linaro.org andersson@kernel.org agross@kernel.org konrad.dybcio@somainline.org linux-arm-msm@vger.kernel.org
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Commit Message

Maxime Chevallier Oct. 21, 2022, 12:45 p.m. UTC 
The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
connected to the CPU through the internal IPQESS Ethernet controller.

Add support for this internal interface, which is internally connected to a
modified version of the QCA8K Ethernet switch.

This Ethernet controller only support a specific internal interface mode
for connection to the switch.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
V4->V5:
 - Reword the commit log
V3->V4:
 - No Changes
V2->V3:
 - No Changes
V1->V2:
 - Added clock and resets
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 46 +++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

Comments

Vladimir Oltean Oct. 21, 2022, 2:20 p.m. UTC | #1 
On Fri, Oct 21, 2022 at 02:45:56PM +0200, Maxime Chevallier wrote:
> @@ -591,6 +592,51 @@ wifi1: wifi@a800000 {
>  			status = "disabled";
>  		};
>  
> +		gmac: ethernet@c080000 {

Pretty random ordering in this dts, you'd expect nodes are sorted by
address...

> +			compatible = "qcom,ipq4019-ess-edma";
> +			reg = <0xc080000 0x8000>;
> +			resets = <&gcc ESS_RESET>;
> +			reset-names = "ess";
> +			clocks = <&gcc GCC_ESS_CLK>;
> +			clock-names = "ess";
> +			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;

32 interrupts, and no interrupt-names? :)

> +
> +			status = "disabled";
> +

Could you drop these 2 blank lines? They aren't generally added between
properties.

> +			phy-mode = "internal";

And the fixed-link from the schema example no?

> +		};
> +
>  		mdio: mdio@90000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -- 
> 2.37.3
>
Krzysztof Kozlowski Oct. 21, 2022, 2:29 p.m. UTC | #2 
On 21/10/2022 10:20, Vladimir Oltean wrote:
> On Fri, Oct 21, 2022 at 02:45:56PM +0200, Maxime Chevallier wrote:
>> @@ -591,6 +592,51 @@ wifi1: wifi@a800000 {
>>  			status = "disabled";
>>  		};
>>  
>> +		gmac: ethernet@c080000 {
> 
> Pretty random ordering in this dts, you'd expect nodes are sorted by
> address...

Good point.

> 
>> +			compatible = "qcom,ipq4019-ess-edma";
>> +			reg = <0xc080000 0x8000>;
>> +			resets = <&gcc ESS_RESET>;
>> +			reset-names = "ess";
>> +			clocks = <&gcc GCC_ESS_CLK>;
>> +			clock-names = "ess";
>> +			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
> 
> 32 interrupts, and no interrupt-names? :)

There is no requirement for names, because entries must be ordered. Also
Linux driver simply does not use them as it is slower to map, then just
by index. For few other Qualcomm drivers we dropped the names as well.

> 
>> +
>> +			status = "disabled";
>> +
> 
> Could you drop these 2 blank lines? They aren't generally added between
> properties.
> 

... and put status at the end.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index b23591110bd2..0092a881dbf4 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -38,6 +38,7 @@  aliases {
 		spi1 = &blsp1_spi2;
 		i2c0 = &blsp1_i2c3;
 		i2c1 = &blsp1_i2c4;
+		ethernet0 = &gmac;
 	};
 
 	cpus {
@@ -591,6 +592,51 @@  wifi1: wifi@a800000 {
 			status = "disabled";
 		};
 
+		gmac: ethernet@c080000 {
+			compatible = "qcom,ipq4019-ess-edma";
+			reg = <0xc080000 0x8000>;
+			resets = <&gcc ESS_RESET>;
+			reset-names = "ess";
+			clocks = <&gcc GCC_ESS_CLK>;
+			clock-names = "ess";
+			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+
+			status = "disabled";
+
+			phy-mode = "internal";
+		};
+
 		mdio: mdio@90000 {
 			#address-cells = <1>;
 			#size-cells = <0>;