| Message ID | 20221026222102.5526-1-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add DG2 OA support | expand |
Thanks Umesh, Is it looking good to land? Looking forward to have this in Mesa upstream. -Lionel On 27/10/2022 01:20, Umesh Nerlige Ramappa wrote: > Add OA format support for DG2 and various fixes for DG2. > > This series has 2 uapi changes listed below: > > 1) drm/i915/perf: Add OAG and OAR formats for DG2 > > DG2 has new OA formats defined that can be selected by the > user. The UMD changes that are consumed by GPUvis are: > https://patchwork.freedesktop.org/patch/504456/?series=107633&rev=5 > > Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893 > > 2) drm/i915/perf: Apply Wa_18013179988 > > DG2 has a bug where the OA timestamp does not tick at the CS timestamp > frequency. Instead it ticks at a multiple that is determined from the > CTC_SHIFT value in RPM_CONFIG. Since the timestamp is used by UMD to > make sense of all the counters in the report, expose the OA timestamp > frequency to the user. The interface is generic and applies to all > platforms. On platforms where the bug is not present, this returns the > CS timestamp frequency. UMD specific changes consumed by GPUvis are: > https://patchwork.freedesktop.org/patch/504464/?series=107633&rev=5 > > Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893 > > v2: > - Add review comments > - Update uapi changes in cover letter > - Drop patches for non-production platforms > drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size > drm/i915/perf: Add Wa_16010703925:dg2 > > - Drop 64-bit OA format changes for now > drm/i915/perf: Parse 64bit report header formats correctly > drm/i915/perf: Add Wa_1608133521:dg2 > > v3: > - Add review comments to patches 02, 04, 05, 14 > - Drop Acks > > v4: > - Add review comments to patch 04 > - Update R-bs > - Add MR links to patches 02 and 12 > > v5: > - Drop unrelated comment > - Rebase and fix MCR reg write > - On pre-gen12, EU flex config is saved/restored in the context image, so > save/restore EU flex config only for gen12. > > v6: > - Fix checkpatch issues > > Test-with: 20221025200709.83314-1-umesh.nerlige.ramappa@intel.com > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > > Lionel Landwerlin (1): > drm/i915/perf: complete programming whitelisting for XEHPSDV > > Umesh Nerlige Ramappa (14): > drm/i915/perf: Fix OA filtering logic for GuC mode > drm/i915/perf: Add 32-bit OAG and OAR formats for DG2 > drm/i915/perf: Fix noa wait predication for DG2 > drm/i915/perf: Determine gen12 oa ctx offset at runtime > drm/i915/perf: Enable bytes per clock reporting in OA > drm/i915/perf: Simply use stream->ctx > drm/i915/perf: Move gt-specific data from i915->perf to gt->perf > drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops > drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers > drm/i915/perf: Store a pointer to oa_format in oa_buffer > drm/i915/perf: Add Wa_1508761755:dg2 > drm/i915/perf: Apply Wa_18013179988 > drm/i915/perf: Save/restore EU flex counters across reset > drm/i915/perf: Enable OA for DG2 > > Vinay Belgaumkar (1): > drm/i915/guc: Support OA when Wa_16011777198 is enabled > > drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 4 + > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + > drivers/gpu/drm/i915/gt/intel_lrc.h | 2 + > drivers/gpu/drm/i915/gt/intel_sseu.c | 4 +- > .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 9 + > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 + > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 66 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 + > drivers/gpu/drm/i915/i915_drv.h | 5 + > drivers/gpu/drm/i915/i915_getparam.c | 3 + > drivers/gpu/drm/i915/i915_pci.c | 2 + > drivers/gpu/drm/i915/i915_perf.c | 576 ++++++++++++++---- > drivers/gpu/drm/i915/i915_perf.h | 2 + > drivers/gpu/drm/i915/i915_perf_oa_regs.h | 6 +- > drivers/gpu/drm/i915/i915_perf_types.h | 47 +- > drivers/gpu/drm/i915/intel_device_info.h | 2 + > drivers/gpu/drm/i915/selftests/i915_perf.c | 16 +- > include/uapi/drm/i915_drm.h | 10 + > 20 files changed, 630 insertions(+), 141 deletions(-) >
On Thu, Oct 27, 2022 at 03:08:41PM +0000, Patchwork wrote: > Patch Details > >Series: Add DG2 OA support (rev11) >URL: [1]https://patchwork.freedesktop.org/series/107584/ >State: failure >Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/index.html > > CI Bug Log - changes from CI_DRM_12304_full -> Patchwork_107584v11_full > >Summary > > FAILURE > > Serious unknown changes coming with Patchwork_107584v11_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_107584v11_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false positives in > CI. > >Participating hosts (11 -> 11) > > No changes in participating hosts > >Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_107584v11_full: > > IGT changes > > Possible regressions > > * igt@perf@global-sseu-config: > > * shard-tglb: [3]PASS -> [4]SKIP > > Suppressed > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * igt@perf@global-sseu-config: > > * {shard-rkl}: [5]PASS -> [6]SKIP > > * {shard-dg1}: [7]PASS -> [8]SKIP The sseu-config feature is only applicable to ICL, for all other platforms, these tests are expected to skip. Thanks, Umesh > >Known issues >
On Thu, Oct 27, 2022 at 12:34:06PM -0700, Umesh Nerlige Ramappa wrote: >On Thu, Oct 27, 2022 at 03:08:41PM +0000, Patchwork wrote: >> Patch Details >> >>Series: Add DG2 OA support (rev11) >>URL: [1]https://patchwork.freedesktop.org/series/107584/ >>State: failure >>Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v11/index.html >> >> CI Bug Log - changes from CI_DRM_12304_full -> Patchwork_107584v11_full >> >>Summary >> >> FAILURE >> >> Serious unknown changes coming with Patchwork_107584v11_full absolutely >> need to be >> verified manually. >> >> If you think the reported changes have nothing to do with the changes >> introduced in Patchwork_107584v11_full, please notify your bug team to >> allow them >> to document this new failure mode, which will reduce false positives in >> CI. >> >>Participating hosts (11 -> 11) >> >> No changes in participating hosts >> >>Possible new issues >> >> Here are the unknown changes that may have been introduced in >> Patchwork_107584v11_full: >> >> IGT changes >> >> Possible regressions >> >> * igt@perf@global-sseu-config: >> >> * shard-tglb: [3]PASS -> [4]SKIP >> >> Suppressed >> >> The following results come from untrusted machines, tests, or statuses. >> They do not affect the overall result. >> >> * igt@perf@global-sseu-config: >> >> * {shard-rkl}: [5]PASS -> [6]SKIP >> >> * {shard-dg1}: [7]PASS -> [8]SKIP > >The sseu-config feature is only applicable to ICL, for all other >platforms, these tests are expected to skip. Revisiting this, I see that the IGT series needs to be fixed to allow these tests to run on gen12. Only gen12.5 onwards these tests are supposed to skip. Thanks, Umesh > >Thanks, >Umesh >> >>Known issues >>
Add OA format support for DG2 and various fixes for DG2. This series has 2 uapi changes listed below: 1) drm/i915/perf: Add OAG and OAR formats for DG2 DG2 has new OA formats defined that can be selected by the user. The UMD changes that are consumed by GPUvis are: https://patchwork.freedesktop.org/patch/504456/?series=107633&rev=5 Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893 2) drm/i915/perf: Apply Wa_18013179988 DG2 has a bug where the OA timestamp does not tick at the CS timestamp frequency. Instead it ticks at a multiple that is determined from the CTC_SHIFT value in RPM_CONFIG. Since the timestamp is used by UMD to make sense of all the counters in the report, expose the OA timestamp frequency to the user. The interface is generic and applies to all platforms. On platforms where the bug is not present, this returns the CS timestamp frequency. UMD specific changes consumed by GPUvis are: https://patchwork.freedesktop.org/patch/504464/?series=107633&rev=5 Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893 v2: - Add review comments - Update uapi changes in cover letter - Drop patches for non-production platforms drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size drm/i915/perf: Add Wa_16010703925:dg2 - Drop 64-bit OA format changes for now drm/i915/perf: Parse 64bit report header formats correctly drm/i915/perf: Add Wa_1608133521:dg2 v3: - Add review comments to patches 02, 04, 05, 14 - Drop Acks v4: - Add review comments to patch 04 - Update R-bs - Add MR links to patches 02 and 12 v5: - Drop unrelated comment - Rebase and fix MCR reg write - On pre-gen12, EU flex config is saved/restored in the context image, so save/restore EU flex config only for gen12. v6: - Fix checkpatch issues Test-with: 20221025200709.83314-1-umesh.nerlige.ramappa@intel.com Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Lionel Landwerlin (1): drm/i915/perf: complete programming whitelisting for XEHPSDV Umesh Nerlige Ramappa (14): drm/i915/perf: Fix OA filtering logic for GuC mode drm/i915/perf: Add 32-bit OAG and OAR formats for DG2 drm/i915/perf: Fix noa wait predication for DG2 drm/i915/perf: Determine gen12 oa ctx offset at runtime drm/i915/perf: Enable bytes per clock reporting in OA drm/i915/perf: Simply use stream->ctx drm/i915/perf: Move gt-specific data from i915->perf to gt->perf drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers drm/i915/perf: Store a pointer to oa_format in oa_buffer drm/i915/perf: Add Wa_1508761755:dg2 drm/i915/perf: Apply Wa_18013179988 drm/i915/perf: Save/restore EU flex counters across reset drm/i915/perf: Enable OA for DG2 Vinay Belgaumkar (1): drm/i915/guc: Support OA when Wa_16011777198 is enabled drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 4 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/gt/intel_lrc.h | 2 + drivers/gpu/drm/i915/gt/intel_sseu.c | 4 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 9 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 66 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 + drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_getparam.c | 3 + drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_perf.c | 576 ++++++++++++++---- drivers/gpu/drm/i915/i915_perf.h | 2 + drivers/gpu/drm/i915/i915_perf_oa_regs.h | 6 +- drivers/gpu/drm/i915/i915_perf_types.h | 47 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/selftests/i915_perf.c | 16 +- include/uapi/drm/i915_drm.h | 10 + 20 files changed, 630 insertions(+), 141 deletions(-)