| Message ID | 20221021082719.18325-11-trevor.wu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ASoC: mediatek: Add support for MT8188 SoC | expand |
On Fri, Oct 21, 2022 at 04:27:17PM +0800, Trevor Wu wrote: > Add mt8188 audio afe document. > > Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> > --- > .../bindings/sound/mt8188-afe-pcm.yaml | 187 ++++++++++++++++++ > 1 file changed, 187 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > > diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > new file mode 100644 > index 000000000000..b2c548c31e4d > --- /dev/null > +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > @@ -0,0 +1,187 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/sound/mt8188-afe-pcm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek AFE PCM controller for mt8188 > + > +maintainers: > + - Trevor Wu <trevor.wu@mediatek.com> > + > +properties: > + compatible: > + const: mediatek,mt8188-afe > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: audiosys > + > + mediatek,topckgen: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: The phandle of the mediatek topckgen controller > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: 26M clock > + - description: audio pll1 clock > + - description: audio pll2 clock > + - description: clock divider for i2si1_mck > + - description: clock divider for i2si2_mck > + - description: clock divider for i2so1_mck > + - description: clock divider for i2so2_mck > + - description: clock divider for dptx_mck > + - description: a1sys hoping clock > + - description: audio intbus clock > + - description: audio hires clock > + - description: audio local bus clock > + - description: mux for dptx_mck > + - description: mux for i2so1_mck > + - description: mux for i2so2_mck > + - description: mux for i2si1_mck > + - description: mux for i2si2_mck > + - description: audio 26m clock > + > + clock-names: > + items: > + - const: clk26m > + - const: apll1_ck > + - const: apll2_ck > + - const: apll12_div0 > + - const: apll12_div1 > + - const: apll12_div2 > + - const: apll12_div3 > + - const: apll12_div9 > + - const: a1sys_hp_sel > + - const: aud_intbus_sel > + - const: audio_h_sel > + - const: audio_local_bus_sel > + - const: dptx_m_sel > + - const: i2so1_m_sel > + - const: i2so2_m_sel > + - const: i2si1_m_sel > + - const: i2si2_m_sel > + - const: adsp_audio_26m > + > +patternProperties: > + "^mediatek,etdm-in[1-2]-chn-disabled$": > + $ref: /schemas/types.yaml#/definitions/uint8-array > + maxItems: 16 > + description: | Don't need '|' > + Specify which input channel should be disabled, so the data of > + specified channel won't be outputted to memory. I'm not clear on what each of the 16 entries represents. What's index 0, 1, 2, etc.? > + items: > + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] maximum: 15 > + > + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": > + description: Specify etdm in mclk output rate for always on case. > + > + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$": > + description: Specify etdm out mclk output rate for always on case. > + > + "^mediatek,etdm-in[1-2]-multi-pin-mode$": > + type: boolean > + description: if present, the etdm data mode is I2S. > + > + "^mediatek,etdm-out[1-3]-multi-pin-mode$": > + type: boolean > + description: if present, the etdm data mode is I2S. > + > + "^mediatek,etdm-in[1-2]-cowork-source$": > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + etdm modules can share the same external clock pin. Specify > + which etdm clock source is required by this etdm in moudule. > + enum: > + - 0 # etdm1_in > + - 1 # etdm2_in > + - 2 # etdm1_out > + - 3 # etdm2_out > + > + "^mediatek,etdm-out[1-2]-cowork-source$": > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + etdm modules can share the same external clock pin. Specify > + which etdm clock source is required by this etdm out moudule. > + enum: > + - 0 # etdm1_in > + - 1 # etdm2_in > + - 2 # etdm1_out > + - 3 # etdm2_out > + > +required: > + - compatible > + - reg > + - interrupts > + - resets > + - reset-names > + - mediatek,topckgen > + - power-domains > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + afe: afe@10b10000 { > + compatible = "mediatek,mt8188-afe"; > + reg = <0x10b10000 0x10000>; > + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; > + resets = <&watchdog 14>; > + reset-names = "audiosys"; > + mediatek,topckgen = <&topckgen>; > + power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO > + clocks = <&clk26m>, > + <&topckgen 72>, //CLK_TOP_APLL1 > + <&topckgen 73>, //CLK_TOP_APLL2 > + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 > + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 > + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 > + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 > + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 > + <&topckgen 83>, //CLK_TOP_A1SYS_HP > + <&topckgen 31>, //CLK_TOP_AUD_INTBUS > + <&topckgen 32>, //CLK_TOP_AUDIO_H > + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS > + <&topckgen 81>, //CLK_TOP_DPTX > + <&topckgen 77>, //CLK_TOP_I2SO1 > + <&topckgen 78>, //CLK_TOP_I2SO2 > + <&topckgen 79>, //CLK_TOP_I2SI1 > + <&topckgen 80>, //CLK_TOP_I2SI2 > + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M > + clock-names = "clk26m", > + "apll1_ck", > + "apll2_ck", > + "apll12_div0", > + "apll12_div1", > + "apll12_div2", > + "apll12_div3", > + "apll12_div9", > + "a1sys_hp_sel", > + "aud_intbus_sel", > + "audio_h_sel", > + "audio_local_bus_sel", > + "dptx_m_sel", > + "i2so1_m_sel", > + "i2so2_m_sel", > + "i2si1_m_sel", > + "i2si2_m_sel", > + "adsp_audio_26m"; It's good if the examples include optional properties so we at least have some validation the schema matches the DTS. > + }; > + > +... > -- > 2.18.0 > >
On 21/10/2022 04:27, Trevor Wu wrote: > Add mt8188 audio afe document. > > Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. > --- > .../bindings/sound/mt8188-afe-pcm.yaml | 187 ++++++++++++++++++ > 1 file changed, 187 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > > diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > new file mode 100644 > index 000000000000..b2c548c31e4d > --- /dev/null > +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml Name matching compatible. Best regards, Krzysztof
On Fri, 2022-10-28 at 20:06 -0400, Krzysztof Kozlowski wrote: > On 21/10/2022 04:27, Trevor Wu wrote: > > Add mt8188 audio afe document. > > > > Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> > > Please use scripts/get_maintainers.pl to get a list of necessary > people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you > base > your patches on recent Linux kernel. > Hi Krzysztof, Thanks for your review first. I did scripts/get_maintainers.pl based on latest broonie for-next tree, but I misunderstood the rule about CC list. That's why I only picked one maintainer for every domain. I will update the CC list in V3. > > --- > > .../bindings/sound/mt8188-afe-pcm.yaml | 187 > > ++++++++++++++++++ > > 1 file changed, 187 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/sound/mt8188- > > afe-pcm.yaml > > > > diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe- > > pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe- > > pcm.yaml > > new file mode 100644 > > index 000000000000..b2c548c31e4d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > > Name matching compatible. > OK, I will update the file name in V3. Thanks, Trevor > Best regards, > Krzysztof >
On Mon, 2022-10-24 at 13:33 -0500, Rob Herring wrote: > On Fri, Oct 21, 2022 at 04:27:17PM +0800, Trevor Wu wrote: > > Add mt8188 audio afe document. > > > > Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> > > --- > > .../bindings/sound/mt8188-afe-pcm.yaml | 187 > > ++++++++++++++++++ > > 1 file changed, 187 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/sound/mt8188- > > afe-pcm.yaml > > > > diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe- > > pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe- > > pcm.yaml > > new file mode 100644 > > index 000000000000..b2c548c31e4d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml > > @@ -0,0 +1,187 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > ..snip > > > > + > > +patternProperties: > > + "^mediatek,etdm-in[1-2]-chn-disabled$": > > + $ref: /schemas/types.yaml#/definitions/uint8-array > > + maxItems: 16 > > + description: | > > Don't need '|' > > > + Specify which input channel should be disabled, so the data > > of > > + specified channel won't be outputted to memory. > > I'm not clear on what each of the 16 entries represents. What's index > 0, > 1, 2, etc.? Hi Rob, Ext Codec -> ETDM_IN -> MEMIF(DMA) -> Memory The maximum channel number of etdm-in is 16. The index matches to the input channel ID. 0 : CH0 1 : CH1 ... 15: CH15 User can config the channel ID they don't want to be outputted to memory in the property. For example, For 4 channels ETDM connection, and the following property is configured. "mediatek,etdm-in1-chn-disabled = <0>;" Received etdm1 input data outputted to memory will be [d0_ch1, d0_ch2, d0_ch3, d1_ch1, d1_ch2, d1_ch3, ...]. CH0 is dropped. > > > + items: > > + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] > > maximum: 15 > > > > + > > + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": > > + description: Specify etdm in mclk output rate for always on > > case. > > + > > + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$": > > + description: Specify etdm out mclk output rate for always on > > case. > > + > > + "^mediatek,etdm-in[1-2]-multi-pin-mode$": > > + type: boolean > > + description: if present, the etdm data mode is I2S. > > + > > + "^mediatek,etdm-out[1-3]-multi-pin-mode$": > > + type: boolean > > + description: if present, the etdm data mode is I2S. > > + > > + "^mediatek,etdm-in[1-2]-cowork-source$": > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: | > > + etdm modules can share the same external clock pin. Specify > > + which etdm clock source is required by this etdm in moudule. > > + enum: > > + - 0 # etdm1_in > > + - 1 # etdm2_in > > + - 2 # etdm1_out > > + - 3 # etdm2_out > > + > > + "^mediatek,etdm-out[1-2]-cowork-source$": > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: | > > + etdm modules can share the same external clock pin. Specify > > + which etdm clock source is required by this etdm out > > moudule. > > + enum: > > + - 0 # etdm1_in > > + - 1 # etdm2_in > > + - 2 # etdm1_out > > + - 3 # etdm2_out > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - resets > > + - reset-names > > + - mediatek,topckgen > > + - power-domains > > + - clocks > > + - clock-names > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + > > + afe: afe@10b10000 { > > + compatible = "mediatek,mt8188-afe"; > > + reg = <0x10b10000 0x10000>; > > + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; > > + resets = <&watchdog 14>; > > + reset-names = "audiosys"; > > + mediatek,topckgen = <&topckgen>; > > + power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO > > + clocks = <&clk26m>, > > + <&topckgen 72>, //CLK_TOP_APLL1 > > + <&topckgen 73>, //CLK_TOP_APLL2 > > + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 > > + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 > > + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 > > + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 > > + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 > > + <&topckgen 83>, //CLK_TOP_A1SYS_HP > > + <&topckgen 31>, //CLK_TOP_AUD_INTBUS > > + <&topckgen 32>, //CLK_TOP_AUDIO_H > > + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS > > + <&topckgen 81>, //CLK_TOP_DPTX > > + <&topckgen 77>, //CLK_TOP_I2SO1 > > + <&topckgen 78>, //CLK_TOP_I2SO2 > > + <&topckgen 79>, //CLK_TOP_I2SI1 > > + <&topckgen 80>, //CLK_TOP_I2SI2 > > + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M > > + clock-names = "clk26m", > > + "apll1_ck", > > + "apll2_ck", > > + "apll12_div0", > > + "apll12_div1", > > + "apll12_div2", > > + "apll12_div3", > > + "apll12_div9", > > + "a1sys_hp_sel", > > + "aud_intbus_sel", > > + "audio_h_sel", > > + "audio_local_bus_sel", > > + "dptx_m_sel", > > + "i2so1_m_sel", > > + "i2so2_m_sel", > > + "i2si1_m_sel", > > + "i2si2_m_sel", > > + "adsp_audio_26m"; > > It's good if the examples include optional properties so we at least > have some validation the schema matches the DTS. > OK, I will put some optional properties in V3. Thanks, Trevor > > + }; > > + > > +... > > -- > > 2.18.0 > > > > > >
diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml new file mode 100644 index 000000000000..b2c548c31e4d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mt8188-afe-pcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AFE PCM controller for mt8188 + +maintainers: + - Trevor Wu <trevor.wu@mediatek.com> + +properties: + compatible: + const: mediatek,mt8188-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + mediatek,topckgen: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the mediatek topckgen controller + + power-domains: + maxItems: 1 + + clocks: + items: + - description: 26M clock + - description: audio pll1 clock + - description: audio pll2 clock + - description: clock divider for i2si1_mck + - description: clock divider for i2si2_mck + - description: clock divider for i2so1_mck + - description: clock divider for i2so2_mck + - description: clock divider for dptx_mck + - description: a1sys hoping clock + - description: audio intbus clock + - description: audio hires clock + - description: audio local bus clock + - description: mux for dptx_mck + - description: mux for i2so1_mck + - description: mux for i2so2_mck + - description: mux for i2si1_mck + - description: mux for i2si2_mck + - description: audio 26m clock + + clock-names: + items: + - const: clk26m + - const: apll1_ck + - const: apll2_ck + - const: apll12_div0 + - const: apll12_div1 + - const: apll12_div2 + - const: apll12_div3 + - const: apll12_div9 + - const: a1sys_hp_sel + - const: aud_intbus_sel + - const: audio_h_sel + - const: audio_local_bus_sel + - const: dptx_m_sel + - const: i2so1_m_sel + - const: i2so2_m_sel + - const: i2si1_m_sel + - const: i2si2_m_sel + - const: adsp_audio_26m + +patternProperties: + "^mediatek,etdm-in[1-2]-chn-disabled$": + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 16 + description: | + Specify which input channel should be disabled, so the data of + specified channel won't be outputted to memory. + items: + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": + description: Specify etdm in mclk output rate for always on case. + + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$": + description: Specify etdm out mclk output rate for always on case. + + "^mediatek,etdm-in[1-2]-multi-pin-mode$": + type: boolean + description: if present, the etdm data mode is I2S. + + "^mediatek,etdm-out[1-3]-multi-pin-mode$": + type: boolean + description: if present, the etdm data mode is I2S. + + "^mediatek,etdm-in[1-2]-cowork-source$": + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm in moudule. + enum: + - 0 # etdm1_in + - 1 # etdm2_in + - 2 # etdm1_out + - 3 # etdm2_out + + "^mediatek,etdm-out[1-2]-cowork-source$": + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + etdm modules can share the same external clock pin. Specify + which etdm clock source is required by this etdm out moudule. + enum: + - 0 # etdm1_in + - 1 # etdm2_in + - 2 # etdm1_out + - 3 # etdm2_out + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - mediatek,topckgen + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + afe: afe@10b10000 { + compatible = "mediatek,mt8188-afe"; + reg = <0x10b10000 0x10000>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&watchdog 14>; + reset-names = "audiosys"; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO + clocks = <&clk26m>, + <&topckgen 72>, //CLK_TOP_APLL1 + <&topckgen 73>, //CLK_TOP_APLL2 + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 + <&topckgen 83>, //CLK_TOP_A1SYS_HP + <&topckgen 31>, //CLK_TOP_AUD_INTBUS + <&topckgen 32>, //CLK_TOP_AUDIO_H + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS + <&topckgen 81>, //CLK_TOP_DPTX + <&topckgen 77>, //CLK_TOP_I2SO1 + <&topckgen 78>, //CLK_TOP_I2SO2 + <&topckgen 79>, //CLK_TOP_I2SI1 + <&topckgen 80>, //CLK_TOP_I2SI2 + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M + clock-names = "clk26m", + "apll1_ck", + "apll2_ck", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div9", + "a1sys_hp_sel", + "aud_intbus_sel", + "audio_h_sel", + "audio_local_bus_sel", + "dptx_m_sel", + "i2so1_m_sel", + "i2so2_m_sel", + "i2si1_m_sel", + "i2si2_m_sel", + "adsp_audio_26m"; + }; + +...
Add mt8188 audio afe document. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> --- .../bindings/sound/mt8188-afe-pcm.yaml | 187 ++++++++++++++++++ 1 file changed, 187 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml