diff mbox series

[1/5] drm/i915/mtl: add initial definitions for GSC CS

Message ID 20221027221554.2638087-2-daniele.ceraolospurio@intel.com (mailing list archive)
State New, archived
Headers show
Series Introduce the GSC CS | expand

Commit Message

Daniele Ceraolo Spurio Oct. 27, 2022, 10:15 p.m. UTC 
Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
 drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 4 files changed, 11 insertions(+)

Comments

Matt Roper Oct. 27, 2022, 11:25 p.m. UTC | #1 
On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> Starting on MTL, the GSC is no longer managed with direct MMIO access,
> but we instead have a dedicated command streamer for it. As a first step
> for adding support for this CS, add the required definitions.
> Note that, although it is now a CS, the GSC retains its old
> class:instance value (OTHER_CLASS instance 6)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Maybe add "Bspec: 65308, 45605" as a reference?

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3b7d750ad054..e0fbfac03979 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>  			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>  		}
>  	},
> +	[GSC0] = {
> +		.class = OTHER_CLASS,
> +		.instance = OTHER_GSC_INSTANCE,
> +		.mmio_bases = {
> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> +		}
> +	},
>  };
>  
>  /**
> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> +	case OTHER_CLASS:
>  		if (GRAPHICS_VER(gt->i915) < 8)
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 6b5d4ea22b67..4fd54fb8810f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -136,6 +136,7 @@ enum intel_engine_id {
>  	CCS2,
>  	CCS3,
>  #define _CCS(n) (CCS0 + (n))
> +	GSC0,
>  	I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 46a174f8aa00..79312b734690 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>  		[COPY_ENGINE_CLASS] = "bcs",
>  		[VIDEO_DECODE_CLASS] = "vcs",
>  		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> +		[OTHER_CLASS] = "other",
>  		[COMPUTE_CLASS] = "ccs",
>  	};
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c0da50c0dc7..d056c3117ef2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -970,6 +970,7 @@
>  #define GEN11_VEBOX2_RING_BASE		0x1d8000
>  #define XEHP_VEBOX3_RING_BASE		0x1e8000
>  #define XEHP_VEBOX4_RING_BASE		0x1f8000
> +#define MTL_GSC_RING_BASE		0x11a000
>  #define GEN12_COMPUTE0_RING_BASE	0x1a000
>  #define GEN12_COMPUTE1_RING_BASE	0x1c000
>  #define GEN12_COMPUTE2_RING_BASE	0x1e000
> -- 
> 2.37.3
>
Matt Roper Oct. 31, 2022, 4:26 p.m. UTC | #2 
On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> Starting on MTL, the GSC is no longer managed with direct MMIO access,
> but we instead have a dedicated command streamer for it. As a first step
> for adding support for this CS, add the required definitions.
> Note that, although it is now a CS, the GSC retains its old
> class:instance value (OTHER_CLASS instance 6)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Now that we have an OTHER_CLASS engine, I think we also need to deal
with the class -> reg mapping table in mmio_invalidate_full().  I think
the register we want is 0xCF04?

Matt

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3b7d750ad054..e0fbfac03979 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>  			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>  		}
>  	},
> +	[GSC0] = {
> +		.class = OTHER_CLASS,
> +		.instance = OTHER_GSC_INSTANCE,
> +		.mmio_bases = {
> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> +		}
> +	},
>  };
>  
>  /**
> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> +	case OTHER_CLASS:
>  		if (GRAPHICS_VER(gt->i915) < 8)
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 6b5d4ea22b67..4fd54fb8810f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -136,6 +136,7 @@ enum intel_engine_id {
>  	CCS2,
>  	CCS3,
>  #define _CCS(n) (CCS0 + (n))
> +	GSC0,
>  	I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 46a174f8aa00..79312b734690 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>  		[COPY_ENGINE_CLASS] = "bcs",
>  		[VIDEO_DECODE_CLASS] = "vcs",
>  		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> +		[OTHER_CLASS] = "other",
>  		[COMPUTE_CLASS] = "ccs",
>  	};
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c0da50c0dc7..d056c3117ef2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -970,6 +970,7 @@
>  #define GEN11_VEBOX2_RING_BASE		0x1d8000
>  #define XEHP_VEBOX3_RING_BASE		0x1e8000
>  #define XEHP_VEBOX4_RING_BASE		0x1f8000
> +#define MTL_GSC_RING_BASE		0x11a000
>  #define GEN12_COMPUTE0_RING_BASE	0x1a000
>  #define GEN12_COMPUTE1_RING_BASE	0x1c000
>  #define GEN12_COMPUTE2_RING_BASE	0x1e000
> -- 
> 2.37.3
>
Daniele Ceraolo Spurio Oct. 31, 2022, 4:43 p.m. UTC | #3 
On 10/31/2022 9:26 AM, Matt Roper wrote:
> On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
>> Starting on MTL, the GSC is no longer managed with direct MMIO access,
>> but we instead have a dedicated command streamer for it. As a first step
>> for adding support for this CS, add the required definitions.
>> Note that, although it is now a CS, the GSC retains its old
>> class:instance value (OTHER_CLASS instance 6)
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
> Now that we have an OTHER_CLASS engine, I think we also need to deal
> with the class -> reg mapping table in mmio_invalidate_full().  I think
> the register we want is 0xCF04?

I missed that. Looks like the the situation is a bit more complex than 
just adding the new register, because on pre-MTL platforms CF04 is the 
compute class invalidation register. On MTL as you said CF04 is marked 
as the GSC CS invalidation register, but I can't find the compute one. 
Do you know if it re-uses the render one or something like that?
Given that there seem to be non-GSC related changes as well, IMO this 
should probably be a separate patch to specifically handle the TLB inval 
changes on MTL.

Daniele

>
> Matt
>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>>   drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>>   drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   4 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 3b7d750ad054..e0fbfac03979 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>>   			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>>   		}
>>   	},
>> +	[GSC0] = {
>> +		.class = OTHER_CLASS,
>> +		.instance = OTHER_GSC_INSTANCE,
>> +		.mmio_bases = {
>> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
>> +		}
>> +	},
>>   };
>>   
>>   /**
>> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>>   	case VIDEO_DECODE_CLASS:
>>   	case VIDEO_ENHANCEMENT_CLASS:
>>   	case COPY_ENGINE_CLASS:
>> +	case OTHER_CLASS:
>>   		if (GRAPHICS_VER(gt->i915) < 8)
>>   			return 0;
>>   		return GEN8_LR_CONTEXT_OTHER_SIZE;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> index 6b5d4ea22b67..4fd54fb8810f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> @@ -136,6 +136,7 @@ enum intel_engine_id {
>>   	CCS2,
>>   	CCS3,
>>   #define _CCS(n) (CCS0 + (n))
>> +	GSC0,
>>   	I915_NUM_ENGINES
>>   #define INVALID_ENGINE ((enum intel_engine_id)-1)
>>   };
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> index 46a174f8aa00..79312b734690 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>>   		[COPY_ENGINE_CLASS] = "bcs",
>>   		[VIDEO_DECODE_CLASS] = "vcs",
>>   		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
>> +		[OTHER_CLASS] = "other",
>>   		[COMPUTE_CLASS] = "ccs",
>>   	};
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 1c0da50c0dc7..d056c3117ef2 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -970,6 +970,7 @@
>>   #define GEN11_VEBOX2_RING_BASE		0x1d8000
>>   #define XEHP_VEBOX3_RING_BASE		0x1e8000
>>   #define XEHP_VEBOX4_RING_BASE		0x1f8000
>> +#define MTL_GSC_RING_BASE		0x11a000
>>   #define GEN12_COMPUTE0_RING_BASE	0x1a000
>>   #define GEN12_COMPUTE1_RING_BASE	0x1c000
>>   #define GEN12_COMPUTE2_RING_BASE	0x1e000
>> -- 
>> 2.37.3
>>
Matt Roper Oct. 31, 2022, 6:36 p.m. UTC | #4 
On Mon, Oct 31, 2022 at 09:43:33AM -0700, Ceraolo Spurio, Daniele wrote:
> 
> 
> On 10/31/2022 9:26 AM, Matt Roper wrote:
> > On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> > > Starting on MTL, the GSC is no longer managed with direct MMIO access,
> > > but we instead have a dedicated command streamer for it. As a first step
> > > for adding support for this CS, add the required definitions.
> > > Note that, although it is now a CS, the GSC retains its old
> > > class:instance value (OTHER_CLASS instance 6)
> > > 
> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Now that we have an OTHER_CLASS engine, I think we also need to deal
> > with the class -> reg mapping table in mmio_invalidate_full().  I think
> > the register we want is 0xCF04?
> 
> I missed that. Looks like the the situation is a bit more complex than just
> adding the new register, because on pre-MTL platforms CF04 is the compute
> class invalidation register. On MTL as you said CF04 is marked as the GSC CS
> invalidation register, but I can't find the compute one. Do you know if it
> re-uses the render one or something like that?
> Given that there seem to be non-GSC related changes as well, IMO this should
> probably be a separate patch to specifically handle the TLB inval changes on
> MTL.

Yeah, makes sense; we can follow up with separate patches for this.

+Cc Fei since he's done a lot of work on TLB invalidation and may know
what happens to compute class invalidation on MTL when the GSC takes
over that register.


Matt

> 
> Daniele
> 
> > 
> > Matt
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
> > >   drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> > >   drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
> > >   drivers/gpu/drm/i915/i915_reg.h              | 1 +
> > >   4 files changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index 3b7d750ad054..e0fbfac03979 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
> > >   			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> > >   		}
> > >   	},
> > > +	[GSC0] = {
> > > +		.class = OTHER_CLASS,
> > > +		.instance = OTHER_GSC_INSTANCE,
> > > +		.mmio_bases = {
> > > +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> > > +		}
> > > +	},
> > >   };
> > >   /**
> > > @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> > >   	case VIDEO_DECODE_CLASS:
> > >   	case VIDEO_ENHANCEMENT_CLASS:
> > >   	case COPY_ENGINE_CLASS:
> > > +	case OTHER_CLASS:
> > >   		if (GRAPHICS_VER(gt->i915) < 8)
> > >   			return 0;
> > >   		return GEN8_LR_CONTEXT_OTHER_SIZE;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 6b5d4ea22b67..4fd54fb8810f 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -136,6 +136,7 @@ enum intel_engine_id {
> > >   	CCS2,
> > >   	CCS3,
> > >   #define _CCS(n) (CCS0 + (n))
> > > +	GSC0,
> > >   	I915_NUM_ENGINES
> > >   #define INVALID_ENGINE ((enum intel_engine_id)-1)
> > >   };
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 46a174f8aa00..79312b734690 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> > >   		[COPY_ENGINE_CLASS] = "bcs",
> > >   		[VIDEO_DECODE_CLASS] = "vcs",
> > >   		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> > > +		[OTHER_CLASS] = "other",
> > >   		[COMPUTE_CLASS] = "ccs",
> > >   	};
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 1c0da50c0dc7..d056c3117ef2 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -970,6 +970,7 @@
> > >   #define GEN11_VEBOX2_RING_BASE		0x1d8000
> > >   #define XEHP_VEBOX3_RING_BASE		0x1e8000
> > >   #define XEHP_VEBOX4_RING_BASE		0x1f8000
> > > +#define MTL_GSC_RING_BASE		0x11a000
> > >   #define GEN12_COMPUTE0_RING_BASE	0x1a000
> > >   #define GEN12_COMPUTE1_RING_BASE	0x1c000
> > >   #define GEN12_COMPUTE2_RING_BASE	0x1e000
> > > -- 
> > > 2.37.3
> > > 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3b7d750ad054..e0fbfac03979 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -244,6 +244,13 @@  static const struct engine_info intel_engines[] = {
 			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
 		}
 	},
+	[GSC0] = {
+		.class = OTHER_CLASS,
+		.instance = OTHER_GSC_INSTANCE,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
+		}
+	},
 };
 
 /**
@@ -324,6 +331,7 @@  u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 	case VIDEO_DECODE_CLASS:
 	case VIDEO_ENHANCEMENT_CLASS:
 	case COPY_ENGINE_CLASS:
+	case OTHER_CLASS:
 		if (GRAPHICS_VER(gt->i915) < 8)
 			return 0;
 		return GEN8_LR_CONTEXT_OTHER_SIZE;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b5d4ea22b67..4fd54fb8810f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -136,6 +136,7 @@  enum intel_engine_id {
 	CCS2,
 	CCS3,
 #define _CCS(n) (CCS0 + (n))
+	GSC0,
 	I915_NUM_ENGINES
 #define INVALID_ENGINE ((enum intel_engine_id)-1)
 };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 46a174f8aa00..79312b734690 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -140,6 +140,7 @@  const char *intel_engine_class_repr(u8 class)
 		[COPY_ENGINE_CLASS] = "bcs",
 		[VIDEO_DECODE_CLASS] = "vcs",
 		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+		[OTHER_CLASS] = "other",
 		[COMPUTE_CLASS] = "ccs",
 	};
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..d056c3117ef2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -970,6 +970,7 @@ 
 #define GEN11_VEBOX2_RING_BASE		0x1d8000
 #define XEHP_VEBOX3_RING_BASE		0x1e8000
 #define XEHP_VEBOX4_RING_BASE		0x1f8000
+#define MTL_GSC_RING_BASE		0x11a000
 #define GEN12_COMPUTE0_RING_BASE	0x1a000
 #define GEN12_COMPUTE1_RING_BASE	0x1c000
 #define GEN12_COMPUTE2_RING_BASE	0x1e000