| Message ID | 20221031111358.3387297-3-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 6964affe65066651eca21e97247d3b7cac5153dc |
| Headers | show |
| Series | arm64: sunxi: h616: Add USB support | expand |
On Mon, 31 Oct 2022 11:13:53 +0000, Andre Przywara wrote: > The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves > some resources from port 2's PHY and HCI IP. In particular the PMU clock > for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL > register of port 2. To allow each USB port to be controlled > independently of port 2, we need a handle to that particular PMU clock > in the *PHY* node, as the HCI and PHY part might be handled by separate > drivers. > > Add that clock to the requirements of the H616 PHY binding, so that a > PHY driver can apply the quirk in isolation, without requiring help from > port 2's HCI driver. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
On 31-10-22, 11:13, Andre Przywara wrote: > The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves > some resources from port 2's PHY and HCI IP. In particular the PMU clock > for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL > register of port 2. To allow each USB port to be controlled > independently of port 2, we need a handle to that particular PMU clock > in the *PHY* node, as the HCI and PHY part might be handled by separate > drivers. > > Add that clock to the requirements of the H616 PHY binding, so that a > PHY driver can apply the quirk in isolation, without requiring help from > port 2's HCI driver. Applied, thanks
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index 77539b4601c24..2df012d13655e 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -36,18 +36,22 @@ properties: - const: pmu3 clocks: + minItems: 4 items: - description: USB OTG PHY bus clock - description: USB Host 0 PHY bus clock - description: USB Host 1 PHY bus clock - description: USB Host 2 PHY bus clock + - description: PMU clock for host port 2 clock-names: + minItems: 4 items: - const: usb0_phy - const: usb1_phy - const: usb2_phy - const: usb3_phy + - const: pmu2_clk resets: items: @@ -96,6 +100,28 @@ required: - resets - reset-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h616-usb-phy + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + else: + properties: + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + additionalProperties: false examples:
The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves some resources from port 2's PHY and HCI IP. In particular the PMU clock for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL register of port 2. To allow each USB port to be controlled independently of port 2, we need a handle to that particular PMU clock in the *PHY* node, as the HCI and PHY part might be handled by separate drivers. Add that clock to the requirements of the H616 PHY binding, so that a PHY driver can apply the quirk in isolation, without requiring help from port 2's HCI driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)