| Message ID | 20221021054922.2753034-1-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/psr: Remove inappropriate DSC slice alignment warning | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Friday, October 21, 2022 8:49 AM > To: Intel-gfx@lists.freedesktop.org > Cc: Hogander, Jouni <jouni.hogander@intel.com>; Souza, Jose > <jose.souza@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Gupta, > Anshuman <anshuman.gupta@intel.com> > Subject: [PATCH] drm/i915/psr: Remove inappropriate DSC slice alignment > warning > > Selective update area is now aligned with DSC slice height when DSC is enabled. > Remove inappropriate warning about missing DSC alignment. > > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Mika Kahola <mika.kahola@intel.com> > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 904a1049eff3..64e9e134fdca 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1678,9 +1678,6 @@ static void > intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c > pipe_clip->y1 -= pipe_clip->y1 % y_alignment; > if (pipe_clip->y2 % y_alignment) > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * > y_alignment; > - > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) > - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment > with DSC\n"); > } > > /* > -- > 2.34.1
On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote: > Selective update area is now aligned with DSC slice height when > DSC is enabled. Remove inappropriate warning about missing DSC > alignment. > > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Mika Kahola <mika.kahola@intel.com> > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 904a1049eff3..64e9e134fdca 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1678,9 +1678,6 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c > pipe_clip->y1 -= pipe_clip->y1 % y_alignment; > if (pipe_clip->y2 % y_alignment) > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; > - > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) > - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); It is necessary check if DSC alignment and PSR2 alignment matches, if not PSR2 can't be enabled. > } > > /*
On Tue, 2022-11-01 at 20:00 +0000, Souza, Jose wrote: > On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote: > > Selective update area is now aligned with DSC slice height when > > DSC is enabled. Remove inappropriate warning about missing DSC > > alignment. > > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > Cc: Mika Kahola <mika.kahola@intel.com> > > > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 904a1049eff3..64e9e134fdca 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1678,9 +1678,6 @@ static void > > intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state > > *c > > pipe_clip->y1 -= pipe_clip->y1 % y_alignment; > > if (pipe_clip->y2 % y_alignment) > > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) > > * y_alignment; > > - > > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state- > > >dsc.compression_enable) > > - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch > > alignment with DSC\n"); > > It is necessary check if DSC alignment and PSR2 alignment matches, if > not PSR2 can't be enabled. This check is there at the begin of intel_psr2_sel_fetch_pipe_alignment: /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ if (crtc_state->dsc.compression_enable && (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) y_alignment = vdsc_cfg->slice_height; For some reason when this got merged warning was still left there. Now just removing the warning as well. > > > } > > > > /* >
On Tue, 2022-11-01 at 20:55 +0000, Hogander, Jouni wrote: > On Tue, 2022-11-01 at 20:00 +0000, Souza, Jose wrote: > > On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote: > > > Selective update area is now aligned with DSC slice height when > > > DSC is enabled. Remove inappropriate warning about missing DSC > > > alignment. > > > > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > > Cc: Mika Kahola <mika.kahola@intel.com> > > > > > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > > > 1 file changed, 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > index 904a1049eff3..64e9e134fdca 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -1678,9 +1678,6 @@ static void > > > intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state > > > *c > > > pipe_clip->y1 -= pipe_clip->y1 % y_alignment; > > > if (pipe_clip->y2 % y_alignment) > > > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) > > > * y_alignment; > > > - > > > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state- > > > > dsc.compression_enable) > > > - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch > > > alignment with DSC\n"); > > > > It is necessary check if DSC alignment and PSR2 alignment matches, if > > not PSR2 can't be enabled. > > This check is there at the begin of > intel_psr2_sel_fetch_pipe_alignment: > > /* ADLP aligns the SU region to vdsc slice height in case dsc is > enabled */ > if (crtc_state->dsc.compression_enable && > (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) > y_alignment = vdsc_cfg->slice_height; This is still wrong. There is no guarantee that required PSR2 alignment matches vdsc_cfg->slice_height. > > For some reason when this got merged warning was still left there. Now > just removing the warning as well. > > > > > > } > > > > > > /* > > >
On Tue, 2022-11-01 at 21:02 +0000, Souza, Jose wrote: > On Tue, 2022-11-01 at 20:55 +0000, Hogander, Jouni wrote: > > On Tue, 2022-11-01 at 20:00 +0000, Souza, Jose wrote: > > > On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote: > > > > Selective update area is now aligned with DSC slice height when > > > > DSC is enabled. Remove inappropriate warning about missing DSC > > > > alignment. > > > > > > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > > > Cc: Mika Kahola <mika.kahola@intel.com> > > > > > > > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > > > > 1 file changed, 3 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > > index 904a1049eff3..64e9e134fdca 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > > @@ -1678,9 +1678,6 @@ static void > > > > intel_psr2_sel_fetch_pipe_alignment(const struct > > > > intel_crtc_state > > > > *c > > > > pipe_clip->y1 -= pipe_clip->y1 % y_alignment; > > > > if (pipe_clip->y2 % y_alignment) > > > > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) > > > > + 1) > > > > * y_alignment; > > > > - > > > > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state- > > > > > dsc.compression_enable) > > > > - drm_warn(&dev_priv->drm, "Missing PSR2 sel > > > > fetch > > > > alignment with DSC\n"); > > > > > > It is necessary check if DSC alignment and PSR2 alignment > > > matches, if > > > not PSR2 can't be enabled. > > > > This check is there at the begin of > > intel_psr2_sel_fetch_pipe_alignment: > > > > /* ADLP aligns the SU region to vdsc slice height in case dsc is > > enabled */ > > if (crtc_state->dsc.compression_enable && > > (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)) > > y_alignment = vdsc_cfg->slice_height; > > This is still wrong. > There is no guarantee that required PSR2 alignment matches vdsc_cfg- > >slice_height. Thank you for pointing this out. Please check "DSC slice/PSR2 SU panel y granularity alignment" patch set. > > > > > For some reason when this got merged warning was still left there. > > Now > > just removing the warning as well. > > > > > > > > > } > > > > > > > > /* > > > > > >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 904a1049eff3..64e9e134fdca 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1678,9 +1678,6 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c pipe_clip->y1 -= pipe_clip->y1 % y_alignment; if (pipe_clip->y2 % y_alignment) pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; - - if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); } /*
Selective update area is now aligned with DSC slice height when DSC is enabled. Remove inappropriate warning about missing DSC alignment. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-)