| Message ID | 20221018-clk-range-checks-fixes-v2-21-f6736dec138e@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: Make determine_rate mandatory for muxes | expand |
On 11/4/22 8:17 AM, Maxime Ripard wrote: > The Davinci DA8xxx cfgchip mux clock implements a mux with a set_parent > hook, but doesn't provide a determine_rate implementation. > > This is a bit odd, since set_parent() is there to, as its name implies, > change the parent of a clock. However, the most likely candidate to > trigger that parent change is a call to clk_set_rate(), with > determine_rate() figuring out which parent is the best suited for a > given rate. > > The other trigger would be a call to clk_set_parent(), but it's far less > used, and it doesn't look like there's any obvious user for that clock. > > So, the set_parent hook is effectively unused, possibly because of an > oversight. However, it could also be an explicit decision by the > original author to avoid any reparenting but through an explicit call to > clk_set_parent(). The parent is defined in the device tree and is not expected to change at runtime, so if I am understanding the patch correctly, setting the CLK_SET_RATE_NO_REPARENT flag seems correct. > > The latter case would be equivalent to setting the flag > CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook > to __clk_mux_determine_rate(). Indeed, if no determine_rate > implementation is provided, clk_round_rate() (through > clk_core_round_rate_nolock()) will call itself on the parent if > CLK_SET_RATE_PARENT is set, and will not change the clock rate > otherwise. __clk_mux_determine_rate() has the exact same behavior when > CLK_SET_RATE_NO_REPARENT is set. > > And if it was an oversight, then we are at least explicit about our > behavior now and it can be further refined down the line. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > --- > drivers/clk/davinci/da8xx-cfgchip.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/davinci/da8xx-cfgchip.c b/drivers/clk/davinci/da8xx-cfgchip.c > index 4103d605e804..c04276bc4051 100644 > --- a/drivers/clk/davinci/da8xx-cfgchip.c > +++ b/drivers/clk/davinci/da8xx-cfgchip.c > @@ -229,6 +229,7 @@ static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw) > } > > static const struct clk_ops da8xx_cfgchip_mux_clk_ops = { > + .determine_rate = __clk_mux_determine_rate, > .set_parent = da8xx_cfgchip_mux_clk_set_parent, > .get_parent = da8xx_cfgchip_mux_clk_get_parent, > }; > @@ -251,7 +252,7 @@ da8xx_cfgchip_mux_clk_register(struct device *dev, > init.ops = &da8xx_cfgchip_mux_clk_ops; > init.parent_names = parent_names; > init.num_parents = 2; > - init.flags = 0; > + init.flags = CLK_SET_RATE_NO_REPARENT; > > mux->hw.init = &init; > mux->regmap = regmap; >
Hi David, On Fri, Nov 04, 2022 at 11:45:17AM -0500, David Lechner wrote: > On 11/4/22 8:17 AM, Maxime Ripard wrote: > > The Davinci DA8xxx cfgchip mux clock implements a mux with a set_parent > > hook, but doesn't provide a determine_rate implementation. > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > change the parent of a clock. However, the most likely candidate to > > trigger that parent change is a call to clk_set_rate(), with > > determine_rate() figuring out which parent is the best suited for a > > given rate. > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > used, and it doesn't look like there's any obvious user for that clock. > > > > So, the set_parent hook is effectively unused, possibly because of an > > oversight. However, it could also be an explicit decision by the > > original author to avoid any reparenting but through an explicit call to > > clk_set_parent(). > > > The parent is defined in the device tree and is not expected to change > at runtime, so if I am understanding the patch correctly, setting the > CLK_SET_RATE_NO_REPARENT flag seems correct. Is that an acked-by/reviewed-by? Thanks! Maxime
On 11/7/22 6:06 AM, Maxime Ripard wrote: > Hi David, > > On Fri, Nov 04, 2022 at 11:45:17AM -0500, David Lechner wrote: >> On 11/4/22 8:17 AM, Maxime Ripard wrote: >>> The Davinci DA8xxx cfgchip mux clock implements a mux with a set_parent >>> hook, but doesn't provide a determine_rate implementation. >>> >>> This is a bit odd, since set_parent() is there to, as its name implies, >>> change the parent of a clock. However, the most likely candidate to >>> trigger that parent change is a call to clk_set_rate(), with >>> determine_rate() figuring out which parent is the best suited for a >>> given rate. >>> >>> The other trigger would be a call to clk_set_parent(), but it's far less >>> used, and it doesn't look like there's any obvious user for that clock. >>> >>> So, the set_parent hook is effectively unused, possibly because of an >>> oversight. However, it could also be an explicit decision by the >>> original author to avoid any reparenting but through an explicit call to >>> clk_set_parent(). >> >> >> The parent is defined in the device tree and is not expected to change >> at runtime, so if I am understanding the patch correctly, setting the >> CLK_SET_RATE_NO_REPARENT flag seems correct. > > Is that an acked-by/reviewed-by? > > Thanks! > Maxime The commit message could be updated to be more certain now, but sure... Acked-by: David Lechner <david@lechnology.com>
diff --git a/drivers/clk/davinci/da8xx-cfgchip.c b/drivers/clk/davinci/da8xx-cfgchip.c index 4103d605e804..c04276bc4051 100644 --- a/drivers/clk/davinci/da8xx-cfgchip.c +++ b/drivers/clk/davinci/da8xx-cfgchip.c @@ -229,6 +229,7 @@ static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw) } static const struct clk_ops da8xx_cfgchip_mux_clk_ops = { + .determine_rate = __clk_mux_determine_rate, .set_parent = da8xx_cfgchip_mux_clk_set_parent, .get_parent = da8xx_cfgchip_mux_clk_get_parent, }; @@ -251,7 +252,7 @@ da8xx_cfgchip_mux_clk_register(struct device *dev, init.ops = &da8xx_cfgchip_mux_clk_ops; init.parent_names = parent_names; init.num_parents = 2; - init.flags = 0; + init.flags = CLK_SET_RATE_NO_REPARENT; mux->hw.init = &init; mux->regmap = regmap;
The Davinci DA8xxx cfgchip mux clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. __clk_mux_determine_rate() has the exact same behavior when CLK_SET_RATE_NO_REPARENT is set. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/clk/davinci/da8xx-cfgchip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)