| Message ID | 20221028133603.18470-11-johan+linaro@kernel.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom-qmp-pcie: add support for sc8280xp | expand |
On 28/10/2022 09:35, Johan Hovold wrote: > The current QMP PCIe PHY bindings are based on the original MSM8996 > binding which provided multiple PHYs per IP block and these in turn were > described by child nodes. > > Later QMP PCIe PHY blocks only provide a single PHY and the remnant > child node does not really reflect the hardware. > > The original MSM8996 binding also ended up describing the individual > register blocks as belonging to either the wrapper node or the PHY child > nodes. > > This is an unnecessary level of detail which has lead to problems when > later IP blocks using different register layouts have been forced to fit > the original mould rather than updating the binding. The bindings are > arguable also incomplete as they only the describe register blocks used > by the current Linux drivers (e.g. does not include the per lane PCS > registers). > > In preparation for adding new bindings for SC8280XP which further > bindings can be based on, rename the current schema file after IPQ8074, > which was the first SoC added to the bindings after MSM8996 (which has > already been split out), and add a reference to the SC8280XP bindings. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > --- Also missing cc devicetree list. Best regards, Krzysztof
On Fri, Oct 28, 2022 at 05:57:01PM -0400, Krzysztof Kozlowski wrote: > On 28/10/2022 09:35, Johan Hovold wrote: > > The current QMP PCIe PHY bindings are based on the original MSM8996 > > binding which provided multiple PHYs per IP block and these in turn were > > described by child nodes. > > > > Later QMP PCIe PHY blocks only provide a single PHY and the remnant > > child node does not really reflect the hardware. > > > > The original MSM8996 binding also ended up describing the individual > > register blocks as belonging to either the wrapper node or the PHY child > > nodes. > > > > This is an unnecessary level of detail which has lead to problems when > > later IP blocks using different register layouts have been forced to fit > > the original mould rather than updating the binding. The bindings are > > arguable also incomplete as they only the describe register blocks used > > by the current Linux drivers (e.g. does not include the per lane PCS > > registers). > > > > In preparation for adding new bindings for SC8280XP which further > > bindings can be based on, rename the current schema file after IPQ8074, > > which was the first SoC added to the bindings after MSM8996 (which has > > already been split out), and add a reference to the SC8280XP bindings. > > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > > --- > > Also missing cc devicetree list. Yes, I know, but as I mentioned in my reply to Rob on the QMP USB series, I do not intend to repost this series unless someone insists as there were no binding-related changes in v4 (or v3). Johan
On 29-10-22, 10:47, Johan Hovold wrote: > On Fri, Oct 28, 2022 at 05:57:01PM -0400, Krzysztof Kozlowski wrote: > > On 28/10/2022 09:35, Johan Hovold wrote: > > > The current QMP PCIe PHY bindings are based on the original MSM8996 > > > binding which provided multiple PHYs per IP block and these in turn were > > > described by child nodes. > > > > > > Later QMP PCIe PHY blocks only provide a single PHY and the remnant > > > child node does not really reflect the hardware. > > > > > > The original MSM8996 binding also ended up describing the individual > > > register blocks as belonging to either the wrapper node or the PHY child > > > nodes. > > > > > > This is an unnecessary level of detail which has lead to problems when > > > later IP blocks using different register layouts have been forced to fit > > > the original mould rather than updating the binding. The bindings are > > > arguable also incomplete as they only the describe register blocks used > > > by the current Linux drivers (e.g. does not include the per lane PCS > > > registers). > > > > > > In preparation for adding new bindings for SC8280XP which further > > > bindings can be based on, rename the current schema file after IPQ8074, > > > which was the first SoC added to the bindings after MSM8996 (which has > > > already been split out), and add a reference to the SC8280XP bindings. > > > > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > > > --- > > > > Also missing cc devicetree list. > > Yes, I know, but as I mentioned in my reply to Rob on the QMP USB > series, I do not intend to repost this series unless someone insists as > there were no binding-related changes in v4 (or v3). It is always better to repost and get that out :-)
On Sat, Nov 05, 2022 at 05:39:42PM +0530, Vinod Koul wrote: > On 29-10-22, 10:47, Johan Hovold wrote: > > On Fri, Oct 28, 2022 at 05:57:01PM -0400, Krzysztof Kozlowski wrote: > > > Also missing cc devicetree list. > > > > Yes, I know, but as I mentioned in my reply to Rob on the QMP USB > > series, I do not intend to repost this series unless someone insists as > > there were no binding-related changes in v4 (or v3). > > It is always better to repost and get that out :-) Yeah, it's just that I was expecting this series to merged the same day, and I didn't want to spam the list in vain. Johan
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml similarity index 96% rename from Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml rename to Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 324ad7d03a38..62045dcfb20c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml# +$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm QMP PHY controller (PCIe) +title: Qualcomm QMP PHY controller (PCIe, IPQ8074) maintainers: - Vinod Koul <vkoul@kernel.org> @@ -13,6 +13,9 @@ description: QMP PHY controller supports physical layer functionality for a number of controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see + qcom,sc8280xp-qmp-pcie-phy.yaml. + properties: compatible: enum: