| Message ID | 20221104170417.232132-3-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC,v3,1/3] dt-bindings: imx6q-pcie: Handle various clock configurations | expand |
On 04/11/2022 18:04, Marek Vasut wrote: > The i.MX6 and i.MX7D does not use block controller to toggle PCIe > reset, hence the PCIe DT description contains three reset entries > on these older SoCs. Add this exception into the binding document. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: NXP Linux Team <linux-imx@nxp.com> > To: devicetree@vger.kernel.org > --- > V2: - Add mx8mq to 3-reset PCIe core variant > - Handle the resets in allOf section > V3: - Reinstate reset: maxItems:3 and add minItems:2 > - Move reset-names back to main section > - The validation no longer works and introduces errors like these: > arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index 5d731aca34b4d..44a1404cbc2c0 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -80,11 +80,13 @@ properties: > - const: pcie_phy > > resets: > + minItems: 2 > maxItems: 3 > description: Phandles to PCIe-related reset lines exposed by SRC > IP block. Additional required by imx7d-pcie and imx8mq-pcie. > > reset-names: > + minItems: 2 > items: > - const: pciephy > - const: apps > @@ -251,6 +253,29 @@ allOf: > maxItems: 1 > power-domain-names: false > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx6q-pcie > + - fsl,imx6sx-pcie > + - fsl,imx6qp-pcie > + - fsl,imx7d-pcie > + - fsl,imx8mq-pcie > + then: > + properties: > + reset-names: > + maxItems: 3 In your patch v2, for such case you explicitly set both minItems and maxItems to the same value. Here you do not. Let's keep both min and max. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 5d731aca34b4d..44a1404cbc2c0 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -80,11 +80,13 @@ properties: - const: pcie_phy resets: + minItems: 2 maxItems: 3 description: Phandles to PCIe-related reset lines exposed by SRC IP block. Additional required by imx7d-pcie and imx8mq-pcie. reset-names: + minItems: 2 items: - const: pciephy - const: apps @@ -251,6 +253,29 @@ allOf: maxItems: 1 power-domain-names: false + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + then: + properties: + reset-names: + maxItems: 3 + else: + properties: + resets: + maxItems: 2 + reset-names: + items: + - const: apps + - const: turnoff + examples: - | #include <dt-bindings/clock/imx6qdl-clock.h>
The i.MX6 and i.MX7D does not use block controller to toggle PCIe reset, hence the PCIe DT description contains three reset entries on these older SoCs. Add this exception into the binding document. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> To: devicetree@vger.kernel.org --- V2: - Add mx8mq to 3-reset PCIe core variant - Handle the resets in allOf section V3: - Reinstate reset: maxItems:3 and add minItems:2 - Move reset-names back to main section - The validation no longer works and introduces errors like these: arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected --- .../bindings/pci/fsl,imx6q-pcie.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+)