| Message ID | 20221107155825.1644604-8-pierre.gondois@arm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 784287950d8613132d3c3fd502906ba844d63166 |
| Headers | show |
| Series | Update cache properties for arm64 DTS | expand |
On 07/11/2022 16:57, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > The 'cache-unified' property should be present if one of the > properties for unified cache is present ('cache-size', ...). > > Update the Device Trees accordingly. Why do you send it again? This was applied. What is more - you have way too many recipients. Mail servers reject it. It's impossible even to reply to it... > cache-sets = <2048>; Best regards, Krzysztof
On 11/7/22 18:55, Krzysztof Kozlowski wrote: > On 07/11/2022 16:57, Pierre Gondois wrote: >> The DeviceTree Specification v0.3 specifies that the cache node >> 'compatible' and 'cache-level' properties are 'required'. Cf. >> s3.8 Multi-level and Shared Cache Nodes >> The 'cache-unified' property should be present if one of the >> properties for unified cache is present ('cache-size', ...). >> >> Update the Device Trees accordingly. > > Why do you send it again? This was applied. > > What is more - you have way too many recipients. Mail servers reject it. > It's impossible even to reply to it... > >> cache-sets = <2048>; > > Best regards, > Krzysztof > Yes, this patch must be dropped. Sorry for the trouble, Regards, Pierre
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bd6a354b9cb5..8619920da4b6 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -226,6 +226,8 @@ cpu7: cpu@3 { cluster_a57_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; @@ -233,6 +235,8 @@ cluster_a57_l2: l2-cache0 { cluster_a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x40000>; cache-line-size = <64>; cache-sets = <256>; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 1cd771c90b47..f378d8629d88 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -107,6 +107,8 @@ cpu_atlas3: cpu@3 { atlas_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>;
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++++ arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 ++ 2 files changed, 6 insertions(+)