| Message ID | 20220728-rpi-analog-tv-properties-v7-22-7072a478c6b3@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: Analog TV Improvements | expand |
Hi Lukas, Maxime and everyone, W dniu 8.11.2022 o 14:17, Lukas Satin pisze: > They are important for retrogaming and connecting TV out to CRT TV or using > emulator. > > I have PS1 that is using PAL-60 for example. > > Can you add 240p and 288p non-interlaced modes for NTSC and PAL, please? To add progressive mode support, at least for the VC4/VEC device that's used on the Raspberry Pi, all that's necessary is a patch like: --- a/drivers/gpu/drm/vc4/vc4_vec.c +++ b/drivers/gpu/drm/vc4/vc4_vec.c @@ -623,7 +623,9 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, VEC_WRITE(VEC_CLMP0_START, 0xac); VEC_WRITE(VEC_CLMP0_END, 0xec); VEC_WRITE(VEC_CONFIG2, - VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS); + VEC_CONFIG2_UV_DIG_DIS | + VEC_CONFIG2_RGB_DIG_DIS | + ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN)); VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD); VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config); and then you can just add custom modes, for example within Xorg: xrandr --newmode 720x240 13.5 720 736 800 858 240 243 246 262 xrandr --newmode 720x288 13.5 720 740 804 864 288 290 293 312 Note that the pixel aspect ratio will be all over the place - unfortunately this is necessary at the driver level, because VC4's VEC does not support pixel clocks other than 13.5 MHz. However, you can fix it by running something like "xrandr --scale-from 320x240" or "xrandr --scale-from 384x288". Other (non-X) applications would need to be adapted to similarly configure DRM scaling. I'm not sure if Maxime wants to introduce any more code like the patch above to facilitate progressive scan support, though (@Maxime: feel free to grab the code from above or anything else from https://github.com/raspberrypi/linux/pull/4406 if you do, however!). We talked recently that the priority is to finally merge existing functionality first, see this message: https://lore.kernel.org/dri-devel/20221027115822.5vd3fqlcpy4gfq5v@houat/ I'm willing to post a couple of follow-up patches to improve things like support for progressive modes or exotic TV norms (such as PAL-M-50 or PAL-N-60) within the VC4 driver once this patchset lands - but I agree with Maxime's point to focus on merging existing functionality first. > Lukas Best regards, Mateusz Kwiatkowski > On Mon, Nov 7, 2022 at 3:19 PM Maxime Ripard <maxime@cerno.tech> wrote: > > From: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com> > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Acked-by: Noralf Trønnes <noralf@tronnes.org> > Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com> > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > --- > Changes in v6: > - Support PAL60 again > --- > drivers/gpu/drm/vc4/vc4_vec.c | 111 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 107 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c > index a828fc6fb776..d23dbad3cbf6 100644 > --- a/drivers/gpu/drm/vc4/vc4_vec.c > +++ b/drivers/gpu/drm/vc4/vc4_vec.c > @@ -46,6 +46,7 @@ > #define VEC_CONFIG0_YDEL(x) ((x) << 26) > #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) > #define VEC_CONFIG0_CDEL(x) ((x) << 24) > +#define VEC_CONFIG0_SECAM_STD BIT(21) > #define VEC_CONFIG0_PBPR_FIL BIT(18) > #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) > #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) > @@ -76,6 +77,27 @@ > #define VEC_SOFT_RESET 0x10c > #define VEC_CLMP0_START 0x144 > #define VEC_CLMP0_END 0x148 > + > +/* > + * These set the color subcarrier frequency > + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. > + * > + * VEC_FREQ1_0 contains the most significant 16-bit half-word, > + * VEC_FREQ3_2 contains the least significant 16-bit half-word. > + * 0x80000000 seems to be equivalent to the pixel clock > + * (which itself is the VEC clock divided by 8). > + * > + * Reference values (with the default pixel clock of 13.5 MHz): > + * > + * NTSC (3579545.[45] Hz) - 0x21F07C1F > + * PAL (4433618.75 Hz) - 0x2A098ACB > + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 > + * PAL-N (3582056.25 Hz) - 0x21F69446 > + * > + * NOTE: For SECAM, it is used as the Dr center frequency, > + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; > + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. > + */ > #define VEC_FREQ3_2 0x180 > #define VEC_FREQ1_0 0x184 > > @@ -118,6 +140,14 @@ > > #define VEC_INTERRUPT_CONTROL 0x190 > #define VEC_INTERRUPT_STATUS 0x194 > + > +/* > + * Db center frequency for SECAM; the clock for this is the same as for > + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. > + * > + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. > + * That is also the default value, so no need to set it explicitly. > + */ > #define VEC_FCW_SECAM_B 0x198 > #define VEC_SECAM_GAIN_VAL 0x19c > > @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { > VC4_VEC_TV_MODE_NTSC_J, > VC4_VEC_TV_MODE_PAL, > VC4_VEC_TV_MODE_PAL_M, > + VC4_VEC_TV_MODE_NTSC_443, > + VC4_VEC_TV_MODE_PAL_60, > + VC4_VEC_TV_MODE_PAL_N, > + VC4_VEC_TV_MODE_SECAM, > }; > > struct vc4_vec_tv_mode { > unsigned int mode; > + u16 expected_htotal; > u32 config0; > u32 config1; > u32 custom_freq; > @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { > static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { > { > .mode = DRM_MODE_TV_MODE_NTSC, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_NTSC_443, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_NTSC_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_NTSC_J, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > { > .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 864, > .config0 = VEC_CONFIG0_PAL_BDGHI_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + /* PAL-60 */ > + .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_PAL_M_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_PAL_M, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_PAL_M_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_PAL_N, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_PAL_N_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + }, > + { > + .mode = DRM_MODE_TV_MODE_SECAM, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_SECAM_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + .custom_freq = 0x29c71c72, > + }, > }; > > static inline const struct vc4_vec_tv_mode * > -vc4_vec_tv_mode_lookup(unsigned int mode) > +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) > { > unsigned int i; > > for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { > const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; > > - if (tv_mode->mode == mode) > + if (tv_mode->mode == mode && > + tv_mode->expected_htotal == htotal) > return tv_mode; > } > > @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) > > static const struct drm_prop_enum_list legacy_tv_mode_names[] = { > { VC4_VEC_TV_MODE_NTSC, "NTSC", }, > + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, > { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, > { VC4_VEC_TV_MODE_PAL, "PAL", }, > + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, > { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, > + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, > + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, > }; > > static enum drm_connector_status > @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_NTSC; > break; > > + case VC4_VEC_TV_MODE_NTSC_443: > + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; > + break; > + > case VC4_VEC_TV_MODE_NTSC_J: > state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; > break; > > case VC4_VEC_TV_MODE_PAL: > + case VC4_VEC_TV_MODE_PAL_60: > state->tv.mode = DRM_MODE_TV_MODE_PAL; > break; > > @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_PAL_M; > break; > > + case VC4_VEC_TV_MODE_PAL_N: > + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; > + break; > + > + case VC4_VEC_TV_MODE_SECAM: > + state->tv.mode = DRM_MODE_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_NTSC; > break; > > + case DRM_MODE_TV_MODE_NTSC_443: > + *val = VC4_VEC_TV_MODE_NTSC_443; > + break; > + > case DRM_MODE_TV_MODE_NTSC_J: > *val = VC4_VEC_TV_MODE_NTSC_J; > break; > @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_PAL_M; > break; > > + case DRM_MODE_TV_MODE_PAL_N: > + *val = VC4_VEC_TV_MODE_PAL_N; > + break; > + > + case DRM_MODE_TV_MODE_SECAM: > + *val = VC4_VEC_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, > struct drm_connector *connector = &vec->connector; > struct drm_connector_state *conn_state = > drm_atomic_get_new_connector_state(state, connector); > + struct drm_display_mode *adjusted_mode = > + &encoder->crtc->state->adjusted_mode; > const struct vc4_vec_tv_mode *tv_mode; > int idx, ret; > > if (!drm_dev_enter(drm, &idx)) > return; > > - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); > + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, > + adjusted_mode->htotal); > if (!tv_mode) > goto err_dev_exit; > > @@ -648,9 +748,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) > > ret = drm_mode_create_tv_properties(drm, > BIT(DRM_MODE_TV_MODE_NTSC) | > + BIT(DRM_MODE_TV_MODE_NTSC_443) | > BIT(DRM_MODE_TV_MODE_NTSC_J) | > BIT(DRM_MODE_TV_MODE_PAL) | > - BIT(DRM_MODE_TV_MODE_PAL_M)); > + BIT(DRM_MODE_TV_MODE_PAL_M) | > + BIT(DRM_MODE_TV_MODE_PAL_N) | > + BIT(DRM_MODE_TV_MODE_SECAM)); > if (ret) > return ret; > > > -- > b4 0.11.0-dev-99e3a >
Hi Maxime, I ran your v7 patchset on my Pi with Xorg, and the mode switching, as well as the preferred mode handling, all work really well now! I just noted that the downstream version of the vc4 driver still has inaccurate field delays in vc4_crtc.c, which causes vertical lines to appear jagged (like here: https://user-images.githubusercontent.com/4499762/112738569-385c3280-8f64-11eb-83c4-d671537af209.png). This has been fixed downstream in https://github.com/raspberrypi/linux/pull/4241/commits/bc093f27bf2613ec93524fdc19e922dd7dd3d800, but I guess that should be upstreamed separately...? Anyway, it's unrelated to the changes made in this patchset, so... I'm not sure if I'm qualified or allowed to do these, but just in case: Tested-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com> (that pretty much applies to parts 19-22 in general, I can respond to those messages as well if you wish) Best regards, Mateusz Kwiatkowski W dniu 7.11.2022 o 15:16, Maxime Ripard pisze: > From: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com> > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Acked-by: Noralf Trønnes <noralf@tronnes.org> > Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com> > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > --- > Changes in v6: > - Support PAL60 again > --- > drivers/gpu/drm/vc4/vc4_vec.c | 111 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 107 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c > index a828fc6fb776..d23dbad3cbf6 100644 > --- a/drivers/gpu/drm/vc4/vc4_vec.c > +++ b/drivers/gpu/drm/vc4/vc4_vec.c > @@ -46,6 +46,7 @@ > #define VEC_CONFIG0_YDEL(x) ((x) << 26) > #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) > #define VEC_CONFIG0_CDEL(x) ((x) << 24) > +#define VEC_CONFIG0_SECAM_STD BIT(21) > #define VEC_CONFIG0_PBPR_FIL BIT(18) > #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) > #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) > @@ -76,6 +77,27 @@ > #define VEC_SOFT_RESET 0x10c > #define VEC_CLMP0_START 0x144 > #define VEC_CLMP0_END 0x148 > + > +/* > + * These set the color subcarrier frequency > + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. > + * > + * VEC_FREQ1_0 contains the most significant 16-bit half-word, > + * VEC_FREQ3_2 contains the least significant 16-bit half-word. > + * 0x80000000 seems to be equivalent to the pixel clock > + * (which itself is the VEC clock divided by 8). > + * > + * Reference values (with the default pixel clock of 13.5 MHz): > + * > + * NTSC (3579545.[45] Hz) - 0x21F07C1F > + * PAL (4433618.75 Hz) - 0x2A098ACB > + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 > + * PAL-N (3582056.25 Hz) - 0x21F69446 > + * > + * NOTE: For SECAM, it is used as the Dr center frequency, > + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; > + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. > + */ > #define VEC_FREQ3_2 0x180 > #define VEC_FREQ1_0 0x184 > > @@ -118,6 +140,14 @@ > > #define VEC_INTERRUPT_CONTROL 0x190 > #define VEC_INTERRUPT_STATUS 0x194 > + > +/* > + * Db center frequency for SECAM; the clock for this is the same as for > + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. > + * > + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. > + * That is also the default value, so no need to set it explicitly. > + */ > #define VEC_FCW_SECAM_B 0x198 > #define VEC_SECAM_GAIN_VAL 0x19c > > @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { > VC4_VEC_TV_MODE_NTSC_J, > VC4_VEC_TV_MODE_PAL, > VC4_VEC_TV_MODE_PAL_M, > + VC4_VEC_TV_MODE_NTSC_443, > + VC4_VEC_TV_MODE_PAL_60, > + VC4_VEC_TV_MODE_PAL_N, > + VC4_VEC_TV_MODE_SECAM, > }; > > struct vc4_vec_tv_mode { > unsigned int mode; > + u16 expected_htotal; > u32 config0; > u32 config1; > u32 custom_freq; > @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { > static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { > { > .mode = DRM_MODE_TV_MODE_NTSC, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_NTSC_443, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_NTSC_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_NTSC_J, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_NTSC_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > { > .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 864, > .config0 = VEC_CONFIG0_PAL_BDGHI_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + /* PAL-60 */ > + .mode = DRM_MODE_TV_MODE_PAL, > + .expected_htotal = 858, > + .config0 = VEC_CONFIG0_PAL_M_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, > + .custom_freq = 0x2a098acb, > + }, > { > .mode = DRM_MODE_TV_MODE_PAL_M, > + .expected_htotal = 858, > .config0 = VEC_CONFIG0_PAL_M_STD, > .config1 = VEC_CONFIG1_C_CVBS_CVBS, > }, > + { > + .mode = DRM_MODE_TV_MODE_PAL_N, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_PAL_N_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + }, > + { > + .mode = DRM_MODE_TV_MODE_SECAM, > + .expected_htotal = 864, > + .config0 = VEC_CONFIG0_SECAM_STD, > + .config1 = VEC_CONFIG1_C_CVBS_CVBS, > + .custom_freq = 0x29c71c72, > + }, > }; > > static inline const struct vc4_vec_tv_mode * > -vc4_vec_tv_mode_lookup(unsigned int mode) > +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) > { > unsigned int i; > > for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { > const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; > > - if (tv_mode->mode == mode) > + if (tv_mode->mode == mode && > + tv_mode->expected_htotal == htotal) > return tv_mode; > } > > @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) > > static const struct drm_prop_enum_list legacy_tv_mode_names[] = { > { VC4_VEC_TV_MODE_NTSC, "NTSC", }, > + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, > { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, > { VC4_VEC_TV_MODE_PAL, "PAL", }, > + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, > { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, > + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, > + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, > }; > > static enum drm_connector_status > @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_NTSC; > break; > > + case VC4_VEC_TV_MODE_NTSC_443: > + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; > + break; > + > case VC4_VEC_TV_MODE_NTSC_J: > state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; > break; > > case VC4_VEC_TV_MODE_PAL: > + case VC4_VEC_TV_MODE_PAL_60: > state->tv.mode = DRM_MODE_TV_MODE_PAL; > break; > > @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, > state->tv.mode = DRM_MODE_TV_MODE_PAL_M; > break; > > + case VC4_VEC_TV_MODE_PAL_N: > + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; > + break; > + > + case VC4_VEC_TV_MODE_SECAM: > + state->tv.mode = DRM_MODE_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_NTSC; > break; > > + case DRM_MODE_TV_MODE_NTSC_443: > + *val = VC4_VEC_TV_MODE_NTSC_443; > + break; > + > case DRM_MODE_TV_MODE_NTSC_J: > *val = VC4_VEC_TV_MODE_NTSC_J; > break; > @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, > *val = VC4_VEC_TV_MODE_PAL_M; > break; > > + case DRM_MODE_TV_MODE_PAL_N: > + *val = VC4_VEC_TV_MODE_PAL_N; > + break; > + > + case DRM_MODE_TV_MODE_SECAM: > + *val = VC4_VEC_TV_MODE_SECAM; > + break; > + > default: > return -EINVAL; > } > @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, > struct drm_connector *connector = &vec->connector; > struct drm_connector_state *conn_state = > drm_atomic_get_new_connector_state(state, connector); > + struct drm_display_mode *adjusted_mode = > + &encoder->crtc->state->adjusted_mode; > const struct vc4_vec_tv_mode *tv_mode; > int idx, ret; > > if (!drm_dev_enter(drm, &idx)) > return; > > - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); > + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, > + adjusted_mode->htotal); > if (!tv_mode) > goto err_dev_exit; > > @@ -648,9 +748,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) > > ret = drm_mode_create_tv_properties(drm, > BIT(DRM_MODE_TV_MODE_NTSC) | > + BIT(DRM_MODE_TV_MODE_NTSC_443) | > BIT(DRM_MODE_TV_MODE_NTSC_J) | > BIT(DRM_MODE_TV_MODE_PAL) | > - BIT(DRM_MODE_TV_MODE_PAL_M)); > + BIT(DRM_MODE_TV_MODE_PAL_M) | > + BIT(DRM_MODE_TV_MODE_PAL_N) | > + BIT(DRM_MODE_TV_MODE_SECAM)); > if (ret) > return ret; > > */pre>
On Wed, Nov 09, 2022 at 05:55:36PM +0100, Lukas Satin wrote: > That's great, I will test it on Ubuntu + Nouveau x86_64 and Batocera-Linux. > > I'm not interested in Raspberry Pi. I see you have some commit in > RaspberryPi/Linux. Will this go to some Nouveau driver, so I can test it on > x86_64 machine? I have some basic experience compiling Linux kernel (nvidia > driver) from 10 years ago. Nouveau is only marginally affected by this patch series. It could leverage the work done here, but it's not part of it and I won't plan to work on it. The RaspberryPi is mentioned because it's the platform that will benefit the most from it, and the main target of that series. > Scaling is not the way to go because I do this to not use scaling. I could > use 640x480 and scale 320x240 to that mode, right? That is what old > retrogaming laptop LCD screens do (you can even enable this in their BIOS). > > More appropriate is to preserve pixel ratio and have some border. So you > mostly select the closest resolution and live with small border on the > edge. Then you can crop it on analog TV using real world dials :-) > > I joined Nouveau developer list here. I don't know why we have like 40 > email recipients here and now we discuss Raspberry. Nouveau is marginally affected by it, so its mailing list is in Cc. Maxime
Hi! On Wed, Nov 09, 2022 at 02:15:29AM +0100, Mateusz Kwiatkowski wrote: > I ran your v7 patchset on my Pi with Xorg, and the mode switching, as well as > the preferred mode handling, all work really well now! Thanks again for all your help > I just noted that the downstream version of the vc4 driver still has inaccurate > field delays in vc4_crtc.c, which causes vertical lines to appear jagged (like > here: https://user-images.githubusercontent.com/4499762/112738569-385c3280-8f64-11eb-83c4-d671537af209.png). > This has been fixed downstream in > https://github.com/raspberrypi/linux/pull/4241/commits/bc093f27bf2613ec93524fdc19e922dd7dd3d800, > but I guess that should be upstreamed separately...? I guess I missed it while rebasing, but yeah, it should definitely be upstreamed. Maxime
diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c index a828fc6fb776..d23dbad3cbf6 100644 --- a/drivers/gpu/drm/vc4/vc4_vec.c +++ b/drivers/gpu/drm/vc4/vc4_vec.c @@ -46,6 +46,7 @@ #define VEC_CONFIG0_YDEL(x) ((x) << 26) #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) #define VEC_CONFIG0_CDEL(x) ((x) << 24) +#define VEC_CONFIG0_SECAM_STD BIT(21) #define VEC_CONFIG0_PBPR_FIL BIT(18) #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) @@ -76,6 +77,27 @@ #define VEC_SOFT_RESET 0x10c #define VEC_CLMP0_START 0x144 #define VEC_CLMP0_END 0x148 + +/* + * These set the color subcarrier frequency + * if VEC_CONFIG1_CUSTOM_FREQ is enabled. + * + * VEC_FREQ1_0 contains the most significant 16-bit half-word, + * VEC_FREQ3_2 contains the least significant 16-bit half-word. + * 0x80000000 seems to be equivalent to the pixel clock + * (which itself is the VEC clock divided by 8). + * + * Reference values (with the default pixel clock of 13.5 MHz): + * + * NTSC (3579545.[45] Hz) - 0x21F07C1F + * PAL (4433618.75 Hz) - 0x2A098ACB + * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 + * PAL-N (3582056.25 Hz) - 0x21F69446 + * + * NOTE: For SECAM, it is used as the Dr center frequency, + * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; + * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. + */ #define VEC_FREQ3_2 0x180 #define VEC_FREQ1_0 0x184 @@ -118,6 +140,14 @@ #define VEC_INTERRUPT_CONTROL 0x190 #define VEC_INTERRUPT_STATUS 0x194 + +/* + * Db center frequency for SECAM; the clock for this is the same as for + * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. + * + * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. + * That is also the default value, so no need to set it explicitly. + */ #define VEC_FCW_SECAM_B 0x198 #define VEC_SECAM_GAIN_VAL 0x19c @@ -197,10 +227,15 @@ enum vc4_vec_tv_mode_id { VC4_VEC_TV_MODE_NTSC_J, VC4_VEC_TV_MODE_PAL, VC4_VEC_TV_MODE_PAL_M, + VC4_VEC_TV_MODE_NTSC_443, + VC4_VEC_TV_MODE_PAL_60, + VC4_VEC_TV_MODE_PAL_N, + VC4_VEC_TV_MODE_SECAM, }; struct vc4_vec_tv_mode { unsigned int mode; + u16 expected_htotal; u32 config0; u32 config1; u32 custom_freq; @@ -236,35 +271,68 @@ static const struct debugfs_reg32 vec_regs[] = { static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { { .mode = DRM_MODE_TV_MODE_NTSC, + .expected_htotal = 858, .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + .mode = DRM_MODE_TV_MODE_NTSC_443, + .expected_htotal = 858, + .config0 = VEC_CONFIG0_NTSC_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x2a098acb, + }, { .mode = DRM_MODE_TV_MODE_NTSC_J, + .expected_htotal = 858, .config0 = VEC_CONFIG0_NTSC_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, { .mode = DRM_MODE_TV_MODE_PAL, + .expected_htotal = 864, .config0 = VEC_CONFIG0_PAL_BDGHI_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + /* PAL-60 */ + .mode = DRM_MODE_TV_MODE_PAL, + .expected_htotal = 858, + .config0 = VEC_CONFIG0_PAL_M_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, + .custom_freq = 0x2a098acb, + }, { .mode = DRM_MODE_TV_MODE_PAL_M, + .expected_htotal = 858, .config0 = VEC_CONFIG0_PAL_M_STD, .config1 = VEC_CONFIG1_C_CVBS_CVBS, }, + { + .mode = DRM_MODE_TV_MODE_PAL_N, + .expected_htotal = 864, + .config0 = VEC_CONFIG0_PAL_N_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS, + }, + { + .mode = DRM_MODE_TV_MODE_SECAM, + .expected_htotal = 864, + .config0 = VEC_CONFIG0_SECAM_STD, + .config1 = VEC_CONFIG1_C_CVBS_CVBS, + .custom_freq = 0x29c71c72, + }, }; static inline const struct vc4_vec_tv_mode * -vc4_vec_tv_mode_lookup(unsigned int mode) +vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) { unsigned int i; for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) { const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i]; - if (tv_mode->mode == mode) + if (tv_mode->mode == mode && + tv_mode->expected_htotal == htotal) return tv_mode; } @@ -273,9 +341,13 @@ vc4_vec_tv_mode_lookup(unsigned int mode) static const struct drm_prop_enum_list legacy_tv_mode_names[] = { { VC4_VEC_TV_MODE_NTSC, "NTSC", }, + { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", }, { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", }, { VC4_VEC_TV_MODE_PAL, "PAL", }, + { VC4_VEC_TV_MODE_PAL_60, "PAL-60", }, { VC4_VEC_TV_MODE_PAL_M, "PAL-M", }, + { VC4_VEC_TV_MODE_PAL_N, "PAL-N", }, + { VC4_VEC_TV_MODE_SECAM, "SECAM", }, }; static enum drm_connector_status @@ -306,11 +378,16 @@ vc4_vec_connector_set_property(struct drm_connector *connector, state->tv.mode = DRM_MODE_TV_MODE_NTSC; break; + case VC4_VEC_TV_MODE_NTSC_443: + state->tv.mode = DRM_MODE_TV_MODE_NTSC_443; + break; + case VC4_VEC_TV_MODE_NTSC_J: state->tv.mode = DRM_MODE_TV_MODE_NTSC_J; break; case VC4_VEC_TV_MODE_PAL: + case VC4_VEC_TV_MODE_PAL_60: state->tv.mode = DRM_MODE_TV_MODE_PAL; break; @@ -318,6 +395,14 @@ vc4_vec_connector_set_property(struct drm_connector *connector, state->tv.mode = DRM_MODE_TV_MODE_PAL_M; break; + case VC4_VEC_TV_MODE_PAL_N: + state->tv.mode = DRM_MODE_TV_MODE_PAL_N; + break; + + case VC4_VEC_TV_MODE_SECAM: + state->tv.mode = DRM_MODE_TV_MODE_SECAM; + break; + default: return -EINVAL; } @@ -341,6 +426,10 @@ vc4_vec_connector_get_property(struct drm_connector *connector, *val = VC4_VEC_TV_MODE_NTSC; break; + case DRM_MODE_TV_MODE_NTSC_443: + *val = VC4_VEC_TV_MODE_NTSC_443; + break; + case DRM_MODE_TV_MODE_NTSC_J: *val = VC4_VEC_TV_MODE_NTSC_J; break; @@ -353,6 +442,14 @@ vc4_vec_connector_get_property(struct drm_connector *connector, *val = VC4_VEC_TV_MODE_PAL_M; break; + case DRM_MODE_TV_MODE_PAL_N: + *val = VC4_VEC_TV_MODE_PAL_N; + break; + + case DRM_MODE_TV_MODE_SECAM: + *val = VC4_VEC_TV_MODE_SECAM; + break; + default: return -EINVAL; } @@ -448,13 +545,16 @@ static void vc4_vec_encoder_enable(struct drm_encoder *encoder, struct drm_connector *connector = &vec->connector; struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, connector); + struct drm_display_mode *adjusted_mode = + &encoder->crtc->state->adjusted_mode; const struct vc4_vec_tv_mode *tv_mode; int idx, ret; if (!drm_dev_enter(drm, &idx)) return; - tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode); + tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, + adjusted_mode->htotal); if (!tv_mode) goto err_dev_exit; @@ -648,9 +748,12 @@ static int vc4_vec_bind(struct device *dev, struct device *master, void *data) ret = drm_mode_create_tv_properties(drm, BIT(DRM_MODE_TV_MODE_NTSC) | + BIT(DRM_MODE_TV_MODE_NTSC_443) | BIT(DRM_MODE_TV_MODE_NTSC_J) | BIT(DRM_MODE_TV_MODE_PAL) | - BIT(DRM_MODE_TV_MODE_PAL_M)); + BIT(DRM_MODE_TV_MODE_PAL_M) | + BIT(DRM_MODE_TV_MODE_PAL_N) | + BIT(DRM_MODE_TV_MODE_SECAM)); if (ret) return ret;