| Message ID | 20221107062413.9642-2-shubhrajyoti.datta@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | edac: xilinx: Added EDAC support for Xilinx DDR controller | expand |
On Mon, 7 Nov 2022 11:54:12 +0530, Shubhrajyoti Datta wrote: > Add device tree bindings for Xilinx Versal EDAC for DDR > controller. > > Applied, thanks! [1/2] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC https://git.kernel.org/krzk/linux-mem-ctrl/c/9342498ca3a499faa2152216ecd644b0888f98d7 Best regards,
On 07/11/2022 07:24, Shubhrajyoti Datta wrote: > Add device tree bindings for Xilinx Versal EDAC for DDR > controller. > > Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- > Applied with fixes in subject - please use prefixes matching the subsystem (memory-controllers) and do not put twice "bindings" (one is enough). Best regards, Krzysztof
On Thu, Nov 10, 2022 at 10:10:56AM +0100, Krzysztof Kozlowski wrote: > On Mon, 7 Nov 2022 11:54:12 +0530, Shubhrajyoti Datta wrote: > > Add device tree bindings for Xilinx Versal EDAC for DDR > > controller. > > > > > > Applied, thanks! If you apply them then I need to merge your tree so that there are no checkpatch warnings about missing devicetree documentation and bla. How about you ACK them and I take them through the EDAC tree after proper review? Thx.
On 10/11/2022 11:01, Borislav Petkov wrote: > On Thu, Nov 10, 2022 at 10:10:56AM +0100, Krzysztof Kozlowski wrote: >> On Mon, 7 Nov 2022 11:54:12 +0530, Shubhrajyoti Datta wrote: >>> Add device tree bindings for Xilinx Versal EDAC for DDR >>> controller. >>> >>> >> >> Applied, thanks! > > If you apply them then I need to merge your tree so that there are no > checkpatch warnings about missing devicetree documentation and bla. Unless you mean some EDAC-tree Patchwork tests, what's in the next matters. Both patches will be in next, so no warnings. If you take it, then all other patches touching these files in this cycle must go via your tree. > > How about you ACK them and I take them through the EDAC tree after > proper review? Sure, I'll provide feedback and drop the patches. Best regards, Krzysztof
On 07/11/2022 07:24, Shubhrajyoti Datta wrote: > Add device tree bindings for Xilinx Versal EDAC for DDR > controller. Use subject prefixes matching the subsystem (git log --oneline -- ...). Subsystem is memory-controllers. Drop redundant, second "bindings" (so "bindings for"). > > Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- Best regards, Krzysztof
On Thu, Nov 10, 2022 at 11:03:43AM +0100, Krzysztof Kozlowski wrote: > Unless you mean some EDAC-tree Patchwork tests, what's in the next > matters. Both patches will be in next, so no warnings. Yeah, that is correct. > If you take it, then all other patches touching these files in this > cycle must go via your tree. Do you expect that happening this cycle? If so, then we can do them this way and I'll ignore those warnings. > Sure, I'll provide feedback and drop the patches. Right, in the past devicetree and driver patches for EDAC drivers have gone together through my tree but if you anticipate conflicts then sure, let's split them. Thx.
On 10/11/2022 11:55, Borislav Petkov wrote: > On Thu, Nov 10, 2022 at 11:03:43AM +0100, Krzysztof Kozlowski wrote: >> Unless you mean some EDAC-tree Patchwork tests, what's in the next >> matters. Both patches will be in next, so no warnings. > > Yeah, that is correct. > >> If you take it, then all other patches touching these files in this >> cycle must go via your tree. > > Do you expect that happening this cycle? > > If so, then we can do them this way and I'll ignore those warnings. > >> Sure, I'll provide feedback and drop the patches. > > Right, in the past devicetree and driver patches for EDAC drivers have > gone together through my tree but if you anticipate conflicts then sure, > let's split them. I don't anticipate more work for current cycle... but I also did not anticipate such in other occasions (e.g. recently Tegra binding headers), so my anticipation is not accurate. :) Best regards, Krzysztof
On Thu, Nov 10, 2022 at 11:57:11AM +0100, Krzysztof Kozlowski wrote: > I don't anticipate more work for current cycle... but I also did not > anticipate such in other occasions (e.g. recently Tegra binding > headers), so my anticipation is not accurate. :) Ok, let's try them your way - you take care of the dtree patches pls and I do the EDAC ones and then we'll see where this goes. Thx.
On 10/11/2022 11:59, Borislav Petkov wrote: > On Thu, Nov 10, 2022 at 11:57:11AM +0100, Krzysztof Kozlowski wrote: >> I don't anticipate more work for current cycle... but I also did not >> anticipate such in other occasions (e.g. recently Tegra binding >> headers), so my anticipation is not accurate. :) > > Ok, let's try them your way - you take care of the dtree patches pls and > I do the EDAC ones and then we'll see where this goes. I already dropped them from my tree, so let's wait for respin and then you can take entire set. Best regards, Krzysztof
On Thu, Nov 10, 2022 at 12:00:34PM +0100, Krzysztof Kozlowski wrote: > I already dropped them from my tree, so let's wait for respin and then > you can take entire set. Or that. Ok, will wait for your Reviewed-by tag then. Thx.
diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + }; + };