diff mbox series

[v2,5/5] PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits

Message ID 20221011184211.18128-6-jim2101024@gmail.com (mailing list archive)
State New, archived
Headers show
Series PCI: brcmstb: Add Multi-MSI and some improvements | expand

Commit Message

Jim Quinlan Oct. 11, 2022, 6:42 p.m. UTC 
Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
the Maximum Payload Size (MPS) are returned in one completion, and data for
PCIe read requests greater than the MPS are split at the specified Read
Completion Boundary setting.

Set RCB_64B so that the Read Compeletion Boundary is 64B.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

Bjorn Helgaas Oct. 13, 2022, 2:12 p.m. UTC | #1 
On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> the Maximum Payload Size (MPS) are returned in one completion, and data for
> PCIe read requests greater than the MPS are split at the specified Read
> Completion Boundary setting.
> 
> Set RCB_64B so that the Read Compeletion Boundary is 64B.

s/Compeletion/Completion/
Jim Quinlan Oct. 14, 2022, 7:16 p.m. UTC | #2 
On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> > Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> > the Maximum Payload Size (MPS) are returned in one completion, and data for
> > PCIe read requests greater than the MPS are split at the specified Read
> > Completion Boundary setting.
> >
> > Set RCB_64B so that the Read Compeletion Boundary is 64B.
>
> s/Compeletion/Completion/

Hi Bjorn,

TIL that checkpatch.pl only flags misspelled words only if they match
its list of misspelled words.
I've modified my checkpatch.pl wrapper script to use aspell to better
address my typos.
At any rate, do you mind if I add some new commits for V3?

Thanks,
Jim Quinlan
Broadcom STB
Bjorn Helgaas Oct. 14, 2022, 7:27 p.m. UTC | #3 
On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> > > Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> > > the Maximum Payload Size (MPS) are returned in one completion, and data for
> > > PCIe read requests greater than the MPS are split at the specified Read
> > > Completion Boundary setting.
> > >
> > > Set RCB_64B so that the Read Compeletion Boundary is 64B.
> >
> > s/Compeletion/Completion/
> 
> Hi Bjorn,
> 
> TIL that checkpatch.pl only flags misspelled words only if they match
> its list of misspelled words.
> I've modified my checkpatch.pl wrapper script to use aspell to better
> address my typos.
> At any rate, do you mind if I add some new commits for V3?

Fine with me, I think Lorenzo will look at these again after v6.1-rc1
is tagged this weekend.

Bjorn
Florian Fainelli Nov. 3, 2022, 6:48 p.m. UTC | #4 
On 10/14/22 12:27, Bjorn Helgaas wrote:
> On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
>> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
>>> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
>>>> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
>>>> the Maximum Payload Size (MPS) are returned in one completion, and data for
>>>> PCIe read requests greater than the MPS are split at the specified Read
>>>> Completion Boundary setting.
>>>>
>>>> Set RCB_64B so that the Read Compeletion Boundary is 64B.
>>>
>>> s/Compeletion/Completion/
>>
>> Hi Bjorn,
>>
>> TIL that checkpatch.pl only flags misspelled words only if they match
>> its list of misspelled words.
>> I've modified my checkpatch.pl wrapper script to use aspell to better
>> address my typos.
>> At any rate, do you mind if I add some new commits for V3?
> 
> Fine with me, I think Lorenzo will look at these again after v6.1-rc1
> is tagged this weekend.

Lorenzo, any chance to get those patches reviewed and/or merged? Thanks!
Jim Quinlan Nov. 3, 2022, 7:43 p.m. UTC | #5 
On Thu, Nov 3, 2022 at 2:49 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> On 10/14/22 12:27, Bjorn Helgaas wrote:
> > On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
> >> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> >>> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> >>>> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> >>>> the Maximum Payload Size (MPS) are returned in one completion, and data for
> >>>> PCIe read requests greater than the MPS are split at the specified Read
> >>>> Completion Boundary setting.
> >>>>
> >>>> Set RCB_64B so that the Read Compeletion Boundary is 64B.
> >>>
> >>> s/Compeletion/Completion/
> >>
> >> Hi Bjorn,
> >>
> >> TIL that checkpatch.pl only flags misspelled words only if they match
> >> its list of misspelled words.
> >> I've modified my checkpatch.pl wrapper script to use aspell to better
> >> address my typos.
> >> At any rate, do you mind if I add some new commits for V3?
> >
> > Fine with me, I think Lorenzo will look at these again after v6.1-rc1
> > is tagged this weekend.
>
> Lorenzo, any chance to get those patches reviewed and/or merged? Thanks!

Oops, I said I would add some commits but I don't have time right now.
  Bjorn  or Lorenzo, could you review what is there and if you accept
the commits can you please make the single spelling correction?  If
not, I will correct the spelling along with any other requested
changes.

Regards,
Jim Quinlan
Broadcom STB
>
> --
> Florian
>
Lorenzo Pieralisi Nov. 11, 2022, 10:26 a.m. UTC | #6 
On Thu, Nov 03, 2022 at 03:43:13PM -0400, Jim Quinlan wrote:
> On Thu, Nov 3, 2022 at 2:49 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
> >
> > On 10/14/22 12:27, Bjorn Helgaas wrote:
> > > On Fri, Oct 14, 2022 at 03:16:35PM -0400, Jim Quinlan wrote:
> > >> On Thu, Oct 13, 2022 at 10:12 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > >>> On Tue, Oct 11, 2022 at 02:42:10PM -0400, Jim Quinlan wrote:
> > >>>> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> > >>>> the Maximum Payload Size (MPS) are returned in one completion, and data for
> > >>>> PCIe read requests greater than the MPS are split at the specified Read
> > >>>> Completion Boundary setting.
> > >>>>
> > >>>> Set RCB_64B so that the Read Compeletion Boundary is 64B.
> > >>>
> > >>> s/Compeletion/Completion/
> > >>
> > >> Hi Bjorn,
> > >>
> > >> TIL that checkpatch.pl only flags misspelled words only if they match
> > >> its list of misspelled words.
> > >> I've modified my checkpatch.pl wrapper script to use aspell to better
> > >> address my typos.
> > >> At any rate, do you mind if I add some new commits for V3?
> > >
> > > Fine with me, I think Lorenzo will look at these again after v6.1-rc1
> > > is tagged this weekend.
> >
> > Lorenzo, any chance to get those patches reviewed and/or merged? Thanks!
> 
> Oops, I said I would add some commits but I don't have time right now.
>   Bjorn  or Lorenzo, could you review what is there and if you accept
> the commits can you please make the single spelling correction?  If
> not, I will correct the spelling along with any other requested
> changes.

I will fix the spelling, reviewing the patches now.

Lorenzo
diff mbox series

Patch

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index e3045f1eadbc..edf283e2b5dd 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -53,6 +53,8 @@ 
 #define PCIE_RC_DL_MDIO_RD_DATA				0x1108
 
 #define PCIE_MISC_MISC_CTRL				0x4008
+#define  PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK	0x80
+#define  PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK	0x400
 #define  PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK		0x1000
 #define  PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK	0x2000
 #define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK	0x300000
@@ -900,11 +902,16 @@  static int brcm_pcie_setup(struct brcm_pcie *pcie)
 	else
 		burst = 0x2; /* 512 bytes */
 
-	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
+	/*
+	 * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN,
+	 * RCB_MPS_MODE, RCB_64B_MODE
+	 */
 	tmp = readl(base + PCIE_MISC_MISC_CTRL);
 	u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
 	u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
 	u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
+	u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK);
+	u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK);
 	writel(tmp, base + PCIE_MISC_MISC_CTRL);
 
 	ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,