Message ID | 20221104092045.17410-3-johan+linaro@kernel.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 33c4e6588e4f018abc43381ee21fe2bed37e34a5 |
Headers | show |
Series | arm64: dts: qcom: sc8280xp: fix UFS reference clocks and PHY nodes | expand |
On 04/11/2022 10:20, Johan Hovold wrote: > Update the UFS PHY nodes to match the new binding. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 49 +++++++++----------------- > 1 file changed, 17 insertions(+), 32 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index e0d0fb6994b5..1b309fa93484 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -896,7 +896,7 @@ ufs_mem_hc: ufs@1d84000 { > "jedec,ufs-2.0"; > reg = <0 0x01d84000 0 0x3000>; > interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > - phys = <&ufs_mem_phy_lanes>; > + phys = <&ufs_mem_phy>; > phy-names = "ufsphy"; > lanes-per-direction = <2>; > #reset-cells = <1>; > @@ -937,27 +937,20 @@ ufs_mem_hc: ufs@1d84000 { > > ufs_mem_phy: phy@1d87000 { > compatible = "qcom,sc8280xp-qmp-ufs-phy"; > - reg = <0 0x01d87000 0 0x1c8>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - clock-names = "ref", > - "ref_aux"; > + reg = <0 0x01d87000 0 0x1000>; > + > clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, > <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > + clock-names = "ref", "ref_aux"; > + > + power-domains = <&gcc UFS_PHY_GDSC>; > > resets = <&ufs_mem_hc 0>; > reset-names = "ufsphy"; > - status = "disabled"; > > - ufs_mem_phy_lanes: phy@1d87400 { > - reg = <0 0x01d87400 0 0x108>, > - <0 0x01d87600 0 0x1e0>, > - <0 0x01d87c00 0 0x1dc>, > - <0 0x01d87800 0 0x108>, > - <0 0x01d87a00 0 0x1e0>; > - #phy-cells = <0>; > - }; > + #phy-cells = <0>; > + > + status = "disabled"; > }; > > ufs_card_hc: ufs@1da4000 { > @@ -965,7 +958,7 @@ ufs_card_hc: ufs@1da4000 { > "jedec,ufs-2.0"; > reg = <0 0x01da4000 0 0x3000>; > interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; > - phys = <&ufs_card_phy_lanes>; > + phys = <&ufs_card_phy>; > phy-names = "ufsphy"; > lanes-per-direction = <2>; > #reset-cells = <1>; > @@ -1005,28 +998,20 @@ ufs_card_hc: ufs@1da4000 { > > ufs_card_phy: phy@1da7000 { > compatible = "qcom,sc8280xp-qmp-ufs-phy"; > - reg = <0 0x01da7000 0 0x1c8>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - clock-names = "ref", > - "ref_aux"; > + reg = <0 0x01da7000 0 0x1000>; > + > clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, > <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; > + clock-names = "ref", "ref_aux"; > + > + power-domains = <&gcc UFS_CARD_GDSC>; > > resets = <&ufs_card_hc 0>; > reset-names = "ufsphy"; > > - status = "disabled"; > + #phy-cells = <0>; > > - ufs_card_phy_lanes: phy@1da7400 { > - reg = <0 0x01da7400 0 0x108>, > - <0 0x01da7600 0 0x1e0>, > - <0 0x01da7c00 0 0x1dc>, > - <0 0x01da7800 0 0x108>, > - <0 0x01da7a00 0 0x1e0>; > - #phy-cells = <0>; > - }; > + status = "disabled"; > }; > > tcsr_mutex: hwlock@1f40000 {
On Fri, Nov 04, 2022 at 10:20:45AM +0100, Johan Hovold wrote: > Update the UFS PHY nodes to match the new binding. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> This is needed in order to boot the sa8540p on linux-next-20221110. Reviewed-by: Brian Masney <bmasney@redhat.com>
On Mon, Nov 14, 2022 at 12:18:24PM -0500, Brian Masney wrote: > On Fri, Nov 04, 2022 at 10:20:45AM +0100, Johan Hovold wrote: > > Update the UFS PHY nodes to match the new binding. > > > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > > This is needed in order to boot the sa8540p on linux-next-20221110. Actually, I take that back... This is not needed to boot on -next. There was a separate problem on the latest -next that I describe at: https://lore.kernel.org/linux-arm-msm/20221114202943.2389489-1-bmasney@redhat.com/T/#u My Reviewed-by still applies for the patch. Brian
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index e0d0fb6994b5..1b309fa93484 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -896,7 +896,7 @@ ufs_mem_hc: ufs@1d84000 { "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x3000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufs_mem_phy_lanes>; + phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; @@ -937,27 +937,20 @@ ufs_mem_hc: ufs@1d84000 { ufs_mem_phy: phy@1d87000 { compatible = "qcom,sc8280xp-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; + reg = <0 0x01d87000 0 0x1000>; + clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; - status = "disabled"; - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; + #phy-cells = <0>; + + status = "disabled"; }; ufs_card_hc: ufs@1da4000 { @@ -965,7 +958,7 @@ ufs_card_hc: ufs@1da4000 { "jedec,ufs-2.0"; reg = <0 0x01da4000 0 0x3000>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufs_card_phy_lanes>; + phys = <&ufs_card_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; @@ -1005,28 +998,20 @@ ufs_card_hc: ufs@1da4000 { ufs_card_phy: phy@1da7000 { compatible = "qcom,sc8280xp-qmp-ufs-phy"; - reg = <0 0x01da7000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; + reg = <0 0x01da7000 0 0x1000>; + clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + power-domains = <&gcc UFS_CARD_GDSC>; resets = <&ufs_card_hc 0>; reset-names = "ufsphy"; - status = "disabled"; + #phy-cells = <0>; - ufs_card_phy_lanes: phy@1da7400 { - reg = <0 0x01da7400 0 0x108>, - <0 0x01da7600 0 0x1e0>, - <0 0x01da7c00 0 0x1dc>, - <0 0x01da7800 0 0x108>, - <0 0x01da7a00 0 0x1e0>; - #phy-cells = <0>; - }; + status = "disabled"; }; tcsr_mutex: hwlock@1f40000 {
Update the UFS PHY nodes to match the new binding. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 49 +++++++++----------------- 1 file changed, 17 insertions(+), 32 deletions(-)