| Message ID | 20221109141852.729246-2-luca.ceresoli@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Tegra20 parallel video input capture | expand |
On 09/11/2022 15:18, luca.ceresoli@bootlin.com wrote: > From: Luca Ceresoli <luca.ceresoli@bootlin.com> > > VIP is the parallel video capture component within the video input > subsystem of Tegra20 (and other Tegra chips, apparently). Subject: drop second, redundant "bindings". > > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > --- > .../display/tegra/nvidia,tegra20-vip.yaml | 64 +++++++++++++++++++ > MAINTAINERS | 7 ++ > 2 files changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > new file mode 100644 > index 000000000000..934dabfd2307 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > @@ -0,0 +1,64 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra VIP (parallel video capture) controller > + > +maintainers: > + - Luca Ceresoli <luca.ceresoli@bootlin.com> > + > +properties: > + $nodename: > + const: vip No need to enforce names in device schemas, especially that this does not look like a generic name. > + > + compatible: > + enum: > + - nvidia,tegra20-vip > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + channel@0: Missing description. > + type: object Do you expect it to grow to more channels? > + > + properties: > + reg: true const: 0 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Port receiving the video stream from the sensor > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Port sending the video stream to the VI > + > + required: > + - port@0 > + - port@1 > + > + additionalProperties: false > + > + required: > + - reg > + - ports > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - "#address-cells" > + - "#size-cells" > + - channel@0 > + > +# see nvidia,tegra20-vi.yaml for an example That file does not have this compatible. At least not on next-20221109. Best regards, Krzysztof
Hello Krzysztof, thanks for the review. I'm glad my error rate on bindings is lower than it used to be before I attended your ELCE talk! ;) On Tue, 15 Nov 2022 13:12:44 +0100 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 09/11/2022 15:18, luca.ceresoli@bootlin.com wrote: > > From: Luca Ceresoli <luca.ceresoli@bootlin.com> > > > > VIP is the parallel video capture component within the video input > > subsystem of Tegra20 (and other Tegra chips, apparently). > > Subject: drop second, redundant "bindings". > > > > > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > > --- > > .../display/tegra/nvidia,tegra20-vip.yaml | 64 +++++++++++++++++++ > > MAINTAINERS | 7 ++ > > 2 files changed, 71 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > > new file mode 100644 > > index 000000000000..934dabfd2307 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > > @@ -0,0 +1,64 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NVIDIA Tegra VIP (parallel video capture) controller > > + > > +maintainers: > > + - Luca Ceresoli <luca.ceresoli@bootlin.com> > > + > > +properties: > > + $nodename: > > + const: vip > > No need to enforce names in device schemas, especially that this does > not look like a generic name. > > > + > > + compatible: > > + enum: > > + - nvidia,tegra20-vip > > + > > + "#address-cells": > > + const: 1 > > + > > + "#size-cells": > > + const: 0 > > + > > + channel@0: > > Missing description. OK, I think this should do: description: parallel video capture interface for the VI > > + type: object > > Do you expect it to grow to more channels? Not on Tegra20, it has one input only, but for other SoCs it's likely. Definitely some (including Tegra20 itself) have multiple CSI-2 inputs, and it's reasonable that this can apply to parallel input too. Is this enough motivation to make room for more channels, or should I remove it since I have no plans to introduce support for other Tegra chips? > > + > > + properties: > > + reg: true > > const: 0 > > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Port receiving the video stream from the sensor > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Port sending the video stream to the VI > > + > > + required: > > + - port@0 > > + - port@1 > > + > > + additionalProperties: false > > + > > + required: > > + - reg > > + - ports > > + > > +unevaluatedProperties: false > > + > > +required: > > + - compatible > > + - "#address-cells" > > + - "#size-cells" > > + - channel@0 > > + > > +# see nvidia,tegra20-vi.yaml for an example > > That file does not have this compatible. At least not on next-20221109. It's added in patch 2. It's a chicken-egg problem, should I add a third patch that adds this line only? ACK for all other comments you wrote.
On 18/11/2022 10:08, Luca Ceresoli wrote: > description: parallel video capture interface for the VI > >>> + type: object >> >> Do you expect it to grow to more channels? > > Not on Tegra20, it has one input only, but for other SoCs it's likely. > Definitely some (including Tegra20 itself) have multiple CSI-2 inputs, > and it's reasonable that this can apply to parallel input too. > > Is this enough motivation to make room for more channels, or should I > remove it since I have no plans to introduce support for other Tegra > chips? The best would be to add some more Tegra SoCs here, so that this @0 makes sense. But I guess the block can be re-used in future, so it could also stay like this. > >>> + >>> + properties: >>> + reg: true >> >> const: 0 >> >>> + >>> + ports: >>> + $ref: /schemas/graph.yaml#/properties/ports >>> + >>> + properties: >>> + port@0: >>> + $ref: /schemas/graph.yaml#/properties/port >>> + description: >>> + Port receiving the video stream from the sensor >>> + >>> + port@1: >>> + $ref: /schemas/graph.yaml#/properties/port >>> + description: >>> + Port sending the video stream to the VI >>> + >>> + required: >>> + - port@0 >>> + - port@1 >>> + >>> + additionalProperties: false >>> + >>> + required: >>> + - reg >>> + - ports >>> + >>> +unevaluatedProperties: false >>> + >>> +required: >>> + - compatible >>> + - "#address-cells" >>> + - "#size-cells" >>> + - channel@0 >>> + >>> +# see nvidia,tegra20-vi.yaml for an example >> >> That file does not have this compatible. At least not on next-20221109. > > It's added in patch 2. It's a chicken-egg problem, should I add a third > patch that adds this line only? > > ACK for all other comments you wrote. It's ok. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml new file mode 100644 index 000000000000..934dabfd2307 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra VIP (parallel video capture) controller + +maintainers: + - Luca Ceresoli <luca.ceresoli@bootlin.com> + +properties: + $nodename: + const: vip + + compatible: + enum: + - nvidia,tegra20-vip + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + channel@0: + type: object + + properties: + reg: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Port receiving the video stream from the sensor + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Port sending the video stream to the VI + + required: + - port@0 + - port@1 + + additionalProperties: false + + required: + - reg + - ports + +unevaluatedProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - channel@0 + +# see nvidia,tegra20-vi.yaml for an example diff --git a/MAINTAINERS b/MAINTAINERS index 046ff06ff97f..b43f6f4e8ccf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20279,6 +20279,13 @@ S: Maintained F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml F: drivers/staging/media/tegra-video/ +TEGRA VIDEO DRIVER FOR TEGRA20 VIP (PARALLEL VIDEO CAPTURE) +M: Luca Ceresoli <luca.ceresoli@bootlin.com> +L: linux-media@vger.kernel.org +L: linux-tegra@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml + TEGRA XUSB PADCTL DRIVER M: JC Kuo <jckuo@nvidia.com> S: Supported