| Message ID | 20221117-b4-amlogic-bindings-convert-v1-11-3f025599b968@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: first batch of dt-schema conversions for Amlogic Meson bindings | expand |
On Fri, 18 Nov 2022 15:33:37 +0100, Neil Armstrong wrote: > Convert the Amlogic Meson AXG DWC PCIE SoC controller bindings to > dt-schema. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > .../devicetree/bindings/pci/amlogic,axg-pcie.yaml | 129 +++++++++++++++++++++ > .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ----------- > 2 files changed, 129 insertions(+), 70 deletions(-) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221117-b4-amlogic-bindings-convert-v1-11-3f025599b968@linaro.org pcie@f9800000: clock-names:0: 'pclk' was expected arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@f9800000: clock-names:1: 'port' was expected arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@f9800000: clock-names:2: 'general' was expected arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@f9800000: Unevaluated properties are not allowed ('clock-names' was unexpected) arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@fa000000: clock-names:0: 'pclk' was expected arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@fa000000: clock-names:1: 'port' was expected arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@fa000000: clock-names:2: 'general' was expected arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@fa000000: Unevaluated properties are not allowed ('clock-names' was unexpected) arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb arch/arm64/boot/dts/amlogic/meson-axg-s400.dtb pcie@fc000000: clock-names:0: 'pclk' was expected arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dtb arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dtb arch/arm64/boot/dts/amlogic/meson-g12a-u200.dtb arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dtb arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dtb arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dtb arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dtb arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dtb arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dtb pcie@fc000000: clock-names:1: 'port' was expected arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dtb arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dtb arch/arm64/boot/dts/amlogic/meson-g12a-u200.dtb arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dtb arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dtb arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dtb arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dtb arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dtb arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dtb pcie@fc000000: clock-names:2: 'general' was expected arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dtb arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dtb arch/arm64/boot/dts/amlogic/meson-g12a-u200.dtb arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dtb arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dtb arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dtb arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dtb arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dtb arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dtb pcie@fc000000: Unevaluated properties are not allowed ('clock-names', 'power-domains' were unexpected) arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dtb arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dtb arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dtb arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dtb arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dtb arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dtb pcie@fc000000: Unevaluated properties are not allowed ('clock-names' was unexpected) arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dtb arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dtb arch/arm64/boot/dts/amlogic/meson-g12a-u200.dtb arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dtb arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dtb arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtb arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dtb arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dtb arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dtb
Hi Neil, On Fri, Nov 18, 2022 at 3:33 PM Neil Armstrong <neil.armstrong@linaro.org> wrote: [...] > + phy-names: > + const: pcie At least SM1 has a PCIe power domain So we need to allow this property as well [...] > +required: > + - compatible clocks and clock-names are missing (you have them in your example though) Best regards, Martin
diff --git a/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml b/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml new file mode 100644 index 000000000000..563a0a3fa6f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson AXG DWC PCIE SoC controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. + +allOf: + - $ref: snps,dw-pcie.yaml# + +# We need a select here so we don't match all nodes with 'snps,dw-pcie' +select: + properties: + compatible: + contains: + enum: + - amlogic,axg-pcie + - amlogic,g12a-pcie + required: + - compatible + +properties: + compatible: + items: + - enum: + - amlogic,axg-pcie + - amlogic,g12a-pcie + - const: snps,dw-pcie + + reg: + items: + - description: External local bus interface registers + - description: Meson designed configuration registers + - description: PCIe configuration space + + reg-names: + items: + - const: elbi + - const: cfg + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe GEN 100M PLL clock + - description: PCIe RC clock gate + - description: PCIe PHY clock + + clock-names: + items: + - const: pclk + - const: port + - const: general + + phys: + maxItems: 1 + + phy-names: + const: pcie + + resets: + items: + - description: Port Reset + - description: Shared APB reset + + reset-names: + items: + - const: port + - const: apb + + num-lanes: + const: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - device_type + - num-lanes + - phys + - phy-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + pcie: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; + clocks = <&pclk>, <&clk_port>, <&clk_phy>; + clock-names = "pclk", "port", "general"; + resets = <&reset_pcie_port>, <&reset_pcie_apb>; + reset-names = "port", "apb"; + phys = <&pcie_phy>; + phy-names = "pcie"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>; + }; +... diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt deleted file mode 100644 index c3a75ac6e59d..000000000000 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ /dev/null @@ -1,70 +0,0 @@ -Amlogic Meson AXG DWC PCIE SoC controller - -Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. - -Additional properties are described here: - -Required properties: -- compatible: - should contain : - - "amlogic,axg-pcie" for AXG SoC Family - - "amlogic,g12a-pcie" for G12A SoC Family - to identify the core. -- reg: - should contain the configuration address space. -- reg-names: Must be - - "elbi" External local bus interface registers - - "cfg" Meson specific registers - - "config" PCIe configuration space -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must include the following entries: - - "pclk" PCIe GEN 100M PLL clock - - "port" PCIe_x(A or B) RC clock gate - - "general" PCIe Phy clock -- resets: phandle to the reset lines. -- reset-names: must contain "port" and "apb" - - "port" Port A or B reset - - "apb" Share APB reset -- phys: should contain a phandle to the PCIE phy -- phy-names: must contain "pcie" - -- device_type: - should be "pci". As specified in snps,dw-pcie.yaml - - -Example configuration: - - pcie: pcie@f9800000 { - compatible = "amlogic,axg-pcie", "snps,dw-pcie"; - reg = <0x0 0xf9800000 0x0 0x400000 - 0x0 0xff646000 0x0 0x2000 - 0x0 0xf9f00000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; - reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; - interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; - - clocks = <&clkc CLKID_USB - &clkc CLKID_PCIE_A - &clkc CLKID_PCIE_CML_EN0>; - clock-names = "general", - "pclk", - "port"; - resets = <&reset RESET_PCIE_A>, - <&reset RESET_PCIE_APB>; - reset-names = "port", - "apb"; - phys = <&pcie_phy>; - phy-names = "pcie"; - };
Convert the Amlogic Meson AXG DWC PCIE SoC controller bindings to dt-schema. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- .../devicetree/bindings/pci/amlogic,axg-pcie.yaml | 129 +++++++++++++++++++++ .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ----------- 2 files changed, 129 insertions(+), 70 deletions(-)