| Message ID | 20221118010627.70576-11-hal.feng@starfivetech.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Basic clock and reset support for StarFive JH7110 RISC-V SoC | expand |
On 18/11/2022 02:06, Hal Feng wrote: > From: Emil Renner Berthing <kernel@esmil.dk> > > Add bindings for the always-on clock and reset generator (AONCRG) on the > JH7110 RISC-V SoC by StarFive Ltd. > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ > 1 file changed, 76 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > new file mode 100644 > index 000000000000..afbb205e294f > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > @@ -0,0 +1,76 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 Always-On Clock and Reset Generator > + > +maintainers: > + - Emil Renner Berthing <kernel@esmil.dk> > + > +properties: > + compatible: > + const: starfive,jh7110-aoncrg > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Main Oscillator > + - description: RTC clock Real Time Clock clock? :) I don't think the input to clock controller is the output of RTC... Best regards, Krzysztof
On Mon, 21 Nov 2022 at 09:49, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 18/11/2022 02:06, Hal Feng wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > Add bindings for the always-on clock and reset generator (AONCRG) on the > > JH7110 RISC-V SoC by StarFive Ltd. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ > > 1 file changed, 76 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > > new file mode 100644 > > index 000000000000..afbb205e294f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > > @@ -0,0 +1,76 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: StarFive JH7110 Always-On Clock and Reset Generator > > + > > +maintainers: > > + - Emil Renner Berthing <kernel@esmil.dk> > > + > > +properties: > > + compatible: > > + const: starfive,jh7110-aoncrg > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Main Oscillator > > + - description: RTC clock > > Real Time Clock clock? :) I don't think the input to clock controller is > the output of RTC... The description is bad, but even the documentation calls it "clk_rtc" even though it's really an optional input from a 32k oscillator. > Best regards, > Krzysztof >
On 21/11/2022 12:38, Emil Renner Berthing wrote: > On Mon, 21 Nov 2022 at 09:49, Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> On 18/11/2022 02:06, Hal Feng wrote: >>> From: Emil Renner Berthing <kernel@esmil.dk> >>> >>> Add bindings for the always-on clock and reset generator (AONCRG) on the >>> JH7110 RISC-V SoC by StarFive Ltd. >>> >>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >>> --- >>> .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ >>> 1 file changed, 76 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >>> new file mode 100644 >>> index 000000000000..afbb205e294f >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >>> @@ -0,0 +1,76 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: StarFive JH7110 Always-On Clock and Reset Generator >>> + >>> +maintainers: >>> + - Emil Renner Berthing <kernel@esmil.dk> >>> + >>> +properties: >>> + compatible: >>> + const: starfive,jh7110-aoncrg >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + clocks: >>> + items: >>> + - description: Main Oscillator >>> + - description: RTC clock >> >> Real Time Clock clock? :) I don't think the input to clock controller is >> the output of RTC... > > The description is bad, but even the documentation calls it "clk_rtc" > even though it's really an optional input from a 32k oscillator. Then description should match reality, not documentation. Documentation is often poor, so if possible better to extend it. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..afbb205e294f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator + - description: RTC clock + - description: RMII reference clock + - description: RGMII RX clock + - description: STG AXI/AHB clock + - description: APB Bus clock + - description: GMAC0 GTX clock + + clock-names: + items: + - const: osc + - const: clk_rtc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus_func + - const: gmac0_gtxclk + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive-jh7110.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive-jh7110.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive-jh7110.h> + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&clk_rtc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; + clock-names = "osc", "clk_rtc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus_func", "gmac0_gtxclk"; + #clock-cells = <1>; + #reset-cells = <1>; + };