| Message ID | 20221031204838.195292-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x | expand |
On 22-10-31 21:48:38, Marek Vasut wrote: > The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used > to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz, > the PLL3 output can be divided down to supply UARTn_ROOT clock with > precise 64 MHz, which divided down further by 16x oversampling factor > used by the i.MX UART core yields 4 Mbdps baud base for the UART IP. > This is useful e.g. for BCM bluetooth chips, which can operate up to > 4 Mbdps. > > Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly. > > Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > Cc: Abel Vesa <abel.vesa@nxp.com> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: linux-arm-kernel@lists.infradead.org > To: linux-clk@vger.kernel.org > --- > drivers/clk/imx/clk-pll14xx.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c > index 1d0f79e9c3467..828336873a98f 100644 > --- a/drivers/clk/imx/clk-pll14xx.c > +++ b/drivers/clk/imx/clk-pll14xx.c > @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { > PLL_1416X_RATE(800000000U, 200, 3, 1), > PLL_1416X_RATE(750000000U, 250, 2, 2), > PLL_1416X_RATE(700000000U, 350, 3, 2), > + PLL_1416X_RATE(640000000U, 320, 3, 2), > PLL_1416X_RATE(600000000U, 300, 3, 2), > + PLL_1416X_RATE(320000000U, 160, 3, 2), > }; > > static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { > -- > 2.35.1 >
On 22-10-31 21:48:38, Marek Vasut wrote: > The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used > to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz, > the PLL3 output can be divided down to supply UARTn_ROOT clock with > precise 64 MHz, which divided down further by 16x oversampling factor > used by the i.MX UART core yields 4 Mbdps baud base for the UART IP. > This is useful e.g. for BCM bluetooth chips, which can operate up to > 4 Mbdps. > > Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly. > > Signed-off-by: Marek Vasut <marex@denx.de> Applied. Thanks. > --- > Cc: Abel Vesa <abel.vesa@nxp.com> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: linux-arm-kernel@lists.infradead.org > To: linux-clk@vger.kernel.org > --- > drivers/clk/imx/clk-pll14xx.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c > index 1d0f79e9c3467..828336873a98f 100644 > --- a/drivers/clk/imx/clk-pll14xx.c > +++ b/drivers/clk/imx/clk-pll14xx.c > @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { > PLL_1416X_RATE(800000000U, 200, 3, 1), > PLL_1416X_RATE(750000000U, 250, 2, 2), > PLL_1416X_RATE(700000000U, 350, 3, 2), > + PLL_1416X_RATE(640000000U, 320, 3, 2), > PLL_1416X_RATE(600000000U, 300, 3, 2), > + PLL_1416X_RATE(320000000U, 160, 3, 2), > }; > > static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { > -- > 2.35.1 >
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1d0f79e9c3467..828336873a98f 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(800000000U, 200, 3, 1), PLL_1416X_RATE(750000000U, 250, 2, 2), PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(320000000U, 160, 3, 2), }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz, the PLL3 output can be divided down to supply UARTn_ROOT clock with precise 64 MHz, which divided down further by 16x oversampling factor used by the i.MX UART core yields 4 Mbdps baud base for the UART IP. This is useful e.g. for BCM bluetooth chips, which can operate up to 4 Mbdps. Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: linux-arm-kernel@lists.infradead.org To: linux-clk@vger.kernel.org --- drivers/clk/imx/clk-pll14xx.c | 2 ++ 1 file changed, 2 insertions(+)