| Message ID | 1669014996-177686-1-git-send-email-shawn.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: dwc: Round up num_ctrls if num_vectors is less than MAX_MSI_IRQS_PER_CTRL | expand |
On Sun, Nov 20, 2022 Shawn Lin <shawn.lin@rock-chips.com> wrote: > > Some SoCs may only support 1 RC with a few MSIs support that the total numver of MSIs is > less than MAX_MSI_IRQS_PER_CTRL. In this case, num_ctrls will be zero which fails setting > up MSI support. Fix it by rounding up num_ctrls to at least one. Hi Shawn Lin, If you find only a single case (1RC with a few MSIs), please set it as one if the divided value is zero. For example, num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; if (num_ctrls < 1) num_ctrls = 1 Best regards, Jingoo Han > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > --- > > drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 39f3b37..2cba2a8 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -61,7 +61,7 @@ irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) > irqreturn_t ret = IRQ_NONE; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); > > for (i = 0; i < num_ctrls; i++) { > status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + > @@ -342,7 +342,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) > > if (!pp->num_vectors) > pp->num_vectors = MSI_DEF_NUM_VECTORS; > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); > > if (!pp->msi_irq[0]) { > pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); > @@ -706,7 +706,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > dw_pcie_setup(pci); > > if (pp->has_msi_ctrl) { > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); > > /* Initialize IRQ Status array */ > for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > -- > 2.7.4 >
On 2022/11/22 7:54, Han Jingoo wrote: > On Sun, Nov 20, 2022 Shawn Lin <shawn.lin@rock-chips.com> wrote: >> >> Some SoCs may only support 1 RC with a few MSIs support that the total numver of MSIs is >> less than MAX_MSI_IRQS_PER_CTRL. In this case, num_ctrls will be zero which fails setting >> up MSI support. Fix it by rounding up num_ctrls to at least one. > > Hi Shawn Lin, > > If you find only a single case (1RC with a few MSIs), please set it as one > if the divided value is zero. > Yes we have one such platform. Will set it to one as your comment. Thanks. > For example, > num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > if (num_ctrls < 1) > num_ctrls = 1 > > Best regards, > Jingoo Han > >> >> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> >> --- >> >> drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index 39f3b37..2cba2a8 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -61,7 +61,7 @@ irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) >> irqreturn_t ret = IRQ_NONE; >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> >> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; >> + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); >> >> for (i = 0; i < num_ctrls; i++) { >> status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + >> @@ -342,7 +342,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) >> >> if (!pp->num_vectors) >> pp->num_vectors = MSI_DEF_NUM_VECTORS; >> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; >> + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); >> >> if (!pp->msi_irq[0]) { >> pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); >> @@ -706,7 +706,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) >> dw_pcie_setup(pci); >> >> if (pp->has_msi_ctrl) { >> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; >> + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); >> >> /* Initialize IRQ Status array */ >> for (ctrl = 0; ctrl < num_ctrls; ctrl++) { >> -- >> 2.7.4 >>
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 39f3b37..2cba2a8 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -61,7 +61,7 @@ irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) irqreturn_t ret = IRQ_NONE; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); for (i = 0; i < num_ctrls; i++) { status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + @@ -342,7 +342,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) if (!pp->num_vectors) pp->num_vectors = MSI_DEF_NUM_VECTORS; - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); if (!pp->msi_irq[0]) { pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); @@ -706,7 +706,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_setup(pci); if (pp->has_msi_ctrl) { - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + num_ctrls = DIV_ROUND_UP(pp->num_vectors, MAX_MSI_IRQS_PER_CTRL); /* Initialize IRQ Status array */ for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
Some SoCs may only support 1 RC with a few MSIs support that the total numver of MSIs is less than MAX_MSI_IRQS_PER_CTRL. In this case, num_ctrls will be zero which fails setting up MSI support. Fix it by rounding up num_ctrls to at least one. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)