| Message ID | 20221104161850.2889894-1-j.neuschaefer@gmx.net (mailing list archive) |
|---|---|
| Headers | show |
| Series | Nuvoton WPCM450 clock and reset driver | expand |
On Fri, 4 Nov 2022 at 16:21, Jonathan Neuschäfer <j.neuschaefer@gmx.net> wrote: > > This series adds support for the clock and reset controller in the Nuvoton > WPCM450 SoC. This means that the clock rates for peripherals will be calculated > automatically based on the clock tree as it was preconfigured by the bootloader. > The 24 MHz dummy clock, that is currently in the devicetree, is no longer needed. > Somewhat unfortunately, this also means that there is a breaking change once > the devicetree starts relying on the clock driver, but I find it acceptable in > this case, because WPCM450 is still at a somewhat early stage. Reviewed-by: Joel Stanley <joel@jms.id.au> > > > Upstreaming plan (although other suggestions are welcome): > > Once reviewed, > > - The ARM/dts changes should go through Joel Stanley's bmc tree I've picked up the standalone patch ("Add clock controller node"). > - The clocksource/timer changes should probably go via Daniel Lezcano and TIP > - The clock controller bindings and driver should go through the clk tree Stephen, do you plan on merging this driver for v6.2? Alternatively, could we get an ack from you and merge this entire series through Arnd, where we have precedent for merging these initial support cross-tree patch sets? > - It probably makes sense to delay the final ARM/dts patch ("ARM: dts: > wpcm450: Switch clocks to clock controller") until next cycle to make > sure it is merged after the clock driver. > > > v5: > - Dropped patch 2 (watchdog: npcm: Enable clock if provided), which > was since merged upstream > - Added patch 2 (clocksource: timer-npcm7xx: Enable timer 1 clock before use) again, > because I wasn't able to find it in linux-next > - Switched the driver to using struct clk_parent_data > - Rebased on 6.1-rc3 > > v4: > - https://lore.kernel.org/lkml/20220610072141.347795-1-j.neuschaefer@gmx.net/ > - Leave WDT clock running during after restart handler > - Fix reset controller initialization > - Dropped patch 2/7 (clocksource: timer-npcm7xx: Enable timer 1 clock before use), > as it was applied by Daniel Lezcano > > v3: > - https://lore.kernel.org/lkml/20220508194333.2170161-1-j.neuschaefer@gmx.net/ > - Changed "refclk" string to "ref" > - Fixed some dead code in the driver > - Added clk_prepare_enable call to the watchdog restart handler > - Added a few review tags > > v2: > - https://lore.kernel.org/lkml/20220429172030.398011-1-j.neuschaefer@gmx.net/ > - various small improvements > > v1: > - https://lore.kernel.org/lkml/20220422183012.444674-1-j.neuschaefer@gmx.net/ > > Jonathan Neuschäfer (6): > dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks > clocksource: timer-npcm7xx: Enable timer 1 clock before use > dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller > ARM: dts: wpcm450: Add clock controller node > clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver > [NOT FOR MERGE] ARM: dts: wpcm450: Switch clocks to clock controller > > .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 +++ > .../bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +- > arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 29 +- > drivers/clk/Makefile | 1 + > drivers/clk/clk-wpcm450.c | 375 ++++++++++++++++++ > drivers/clocksource/timer-npcm7xx.c | 10 + > drivers/reset/Kconfig | 2 +- > .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 ++++ > 8 files changed, 549 insertions(+), 9 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > create mode 100644 drivers/clk/clk-wpcm450.c > create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h > > -- > 2.35.1 >
On 22/11/2022 02:40, Joel Stanley wrote: > On Fri, 4 Nov 2022 at 16:21, Jonathan Neuschäfer <j.neuschaefer@gmx.net> wrote: >> >> This series adds support for the clock and reset controller in the Nuvoton >> WPCM450 SoC. This means that the clock rates for peripherals will be calculated >> automatically based on the clock tree as it was preconfigured by the bootloader. >> The 24 MHz dummy clock, that is currently in the devicetree, is no longer needed. >> Somewhat unfortunately, this also means that there is a breaking change once >> the devicetree starts relying on the clock driver, but I find it acceptable in >> this case, because WPCM450 is still at a somewhat early stage. > > Reviewed-by: Joel Stanley <joel@jms.id.au> > >> >> >> Upstreaming plan (although other suggestions are welcome): >> >> Once reviewed, >> >> - The ARM/dts changes should go through Joel Stanley's bmc tree > > I've picked up the standalone patch ("Add clock controller node"). > >> - The clocksource/timer changes should probably go via Daniel Lezcano and TIP I picked the timer change along with the binding
This series adds support for the clock and reset controller in the Nuvoton WPCM450 SoC. This means that the clock rates for peripherals will be calculated automatically based on the clock tree as it was preconfigured by the bootloader. The 24 MHz dummy clock, that is currently in the devicetree, is no longer needed. Somewhat unfortunately, this also means that there is a breaking change once the devicetree starts relying on the clock driver, but I find it acceptable in this case, because WPCM450 is still at a somewhat early stage. Upstreaming plan (although other suggestions are welcome): Once reviewed, - The ARM/dts changes should go through Joel Stanley's bmc tree - The clocksource/timer changes should probably go via Daniel Lezcano and TIP - The clock controller bindings and driver should go through the clk tree - It probably makes sense to delay the final ARM/dts patch ("ARM: dts: wpcm450: Switch clocks to clock controller") until next cycle to make sure it is merged after the clock driver. v5: - Dropped patch 2 (watchdog: npcm: Enable clock if provided), which was since merged upstream - Added patch 2 (clocksource: timer-npcm7xx: Enable timer 1 clock before use) again, because I wasn't able to find it in linux-next - Switched the driver to using struct clk_parent_data - Rebased on 6.1-rc3 v4: - https://lore.kernel.org/lkml/20220610072141.347795-1-j.neuschaefer@gmx.net/ - Leave WDT clock running during after restart handler - Fix reset controller initialization - Dropped patch 2/7 (clocksource: timer-npcm7xx: Enable timer 1 clock before use), as it was applied by Daniel Lezcano v3: - https://lore.kernel.org/lkml/20220508194333.2170161-1-j.neuschaefer@gmx.net/ - Changed "refclk" string to "ref" - Fixed some dead code in the driver - Added clk_prepare_enable call to the watchdog restart handler - Added a few review tags v2: - https://lore.kernel.org/lkml/20220429172030.398011-1-j.neuschaefer@gmx.net/ - various small improvements v1: - https://lore.kernel.org/lkml/20220422183012.444674-1-j.neuschaefer@gmx.net/ Jonathan Neuschäfer (6): dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks clocksource: timer-npcm7xx: Enable timer 1 clock before use dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller ARM: dts: wpcm450: Add clock controller node clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver [NOT FOR MERGE] ARM: dts: wpcm450: Switch clocks to clock controller .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 +++ .../bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 29 +- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 375 ++++++++++++++++++ drivers/clocksource/timer-npcm7xx.c | 10 + drivers/reset/Kconfig | 2 +- .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 ++++ 8 files changed, 549 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 drivers/clk/clk-wpcm450.c create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1