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[v2,00/38] arm64/sysreg: Convert aarch32 id regs

Message ID 20221130171637.718182-1-james.morse@arm.com (mailing list archive)
Headers show
Series arm64/sysreg: Convert aarch32 id regs | expand

Message

James Morse Nov. 30, 2022, 5:15 p.m. UTC 
Hello!

Changes since the v1
 * Duplicate definition muck up in patch 29 fixed.
 * Rebased onto arm64/for-next/sysregs, which is just rc4.

---

To cleanup an erratum affecting aarch32, I wanted a mask for an id register.
This would have been quick to add, but the right thing to do is to convert
that register to automatic generation. If I was going that far, I may as
well do the lot...

Thanks to Mark Brown for reviewing all this - it was mind numbing to write,
I'm sure its even worse to review!

This will conflict with Amit's series that adds new HWCAPs for 32bit.
Let me know what I should rebase this onto.

The patch that changes the size of the fields in the middle of the series
is the most interesting thing. I also discovered that the tools accept
'0b002' as a value, and it doesn't mind duplicate entries.

This series is based on v6.1-rc4, and can be retrieved from:
https://git.kernel.org/pub/scm/linux/kernel/git/morse/linux.git arm64/generated_sysreg/a32/v2

James Morse (38):
  arm64/sysreg: Standardise naming for ID_MMFR0_EL1
  arm64/sysreg: Standardise naming for ID_MMFR4_EL1
  arm64/sysreg: Standardise naming for ID_MMFR5_EL1
  arm64/sysreg: Standardise naming for ID_ISAR0_EL1
  arm64/sysreg: Standardise naming for ID_ISAR4_EL1
  arm64/sysreg: Standardise naming for ID_ISAR5_EL1
  arm64/sysreg: Standardise naming for ID_ISAR6_EL1
  arm64/sysreg: Standardise naming for ID_PFR0_EL1
  arm64/sysreg: Standardise naming for ID_PFR1_EL1
  arm64/sysreg: Standardise naming for ID_PFR2_EL1
  arm64/sysreg: Standardise naming for ID_DFR0_EL1
  arm64/sysreg: Standardise naming for ID_DFR1_EL1
  arm64/sysreg: Standardise naming for MVFR0_EL1
  arm64/sysreg: Standardise naming for MVFR1_EL1
  arm64/sysreg: Standardise naming for MVFR2_EL1
  arm64/sysreg: Extend the maximum width of a register and symbol name
  arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
  arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
  arm64/sysreg: Convert MVFR0_EL1 to automatic generation
  arm64/sysreg: Convert MVFR1_EL1 to automatic generation
  arm64/sysreg: Convert MVFR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
  arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation

 arch/arm64/include/asm/sysreg.h | 134 +-----
 arch/arm64/kernel/cpufeature.c  | 208 ++++-----
 arch/arm64/kvm/sys_regs.c       |   4 +-
 arch/arm64/tools/gen-sysreg.awk |   2 +-
 arch/arm64/tools/sysreg         | 754 ++++++++++++++++++++++++++++++++
 5 files changed, 862 insertions(+), 240 deletions(-)

Comments

Will Deacon Dec. 1, 2022, 5 p.m. UTC | #1 
Hi James,

On Wed, Nov 30, 2022 at 05:15:59PM +0000, James Morse wrote:
> Changes since the v1
>  * Duplicate definition muck up in patch 29 fixed.
>  * Rebased onto arm64/for-next/sysregs, which is just rc4.
> 
> ---
> 
> To cleanup an erratum affecting aarch32, I wanted a mask for an id register.
> This would have been quick to add, but the right thing to do is to convert
> that register to automatic generation. If I was going that far, I may as
> well do the lot...

So with this applied, we have a couple of duplicate definitions from
sysregs.h (ID_DFR1_EL1_MTPMU_SHIFT and GMID_EL1_BS_SHIFT). I think the
latter was probably even there before. We also have GMID_EL1_BS_SIZE
vs GMID_EL1_BS_WIDTH.

Mind if I clean that as a patch on top up as per below?

Will

--->8

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3350fcdbde08..097488cee174 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -667,8 +667,6 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-#define ID_DFR1_EL1_MTPMU_SHIFT                0
-
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN4_SHIFT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
@@ -719,10 +717,6 @@
 #define SYS_RGSR_EL1_SEED_SHIFT        8
 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
 
-/* GMID_EL1 field definitions */
-#define GMID_EL1_BS_SHIFT      0
-#define GMID_EL1_BS_SIZE       4
-
 /* TFSR{,E0}_EL1 bit definitions */
 #define SYS_TFSR_EL1_TF0_SHIFT 0
 #define SYS_TFSR_EL1_TF1_SHIFT 1
diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S
index 1b7c93ae7e63..5018ac03b6bf 100644
--- a/arch/arm64/lib/mte.S
+++ b/arch/arm64/lib/mte.S
@@ -18,7 +18,7 @@
  */
        .macro  multitag_transfer_size, reg, tmp
        mrs_s   \reg, SYS_GMID_EL1
-       ubfx    \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_SIZE
+       ubfx    \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_WIDTH
        mov     \tmp, #4
        lsl     \reg, \tmp, \reg
        .endm
Will Deacon Dec. 2, 2022, 11:17 a.m. UTC | #2 
[+Marc]

On Wed, 30 Nov 2022 17:15:59 +0000, James Morse wrote:
> Changes since the v1
>  * Duplicate definition muck up in patch 29 fixed.
>  * Rebased onto arm64/for-next/sysregs, which is just rc4.
> 

Applied to arm64 (for-next/sysregs), thanks!

Note that this conflicts with Marc's PMU rework in the kvmarm tree in
slightly annoying ways (things like "IMP_DEF" => "IMPDEF"). I've had a
crack at resolving that at the end of this email.

[01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1
        https://git.kernel.org/arm64/c/37622bae3db3
[02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1
        https://git.kernel.org/arm64/c/5ea1534ec320
[03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1
        https://git.kernel.org/arm64/c/7b24177c631d
[04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1
        https://git.kernel.org/arm64/c/52b3dc559a4c
[05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1
        https://git.kernel.org/arm64/c/3f08e378f00e
[06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1
        https://git.kernel.org/arm64/c/816c8638d8c6
[07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1
        https://git.kernel.org/arm64/c/eef4344f779f
[08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1
        https://git.kernel.org/arm64/c/e0bf98fef3fd
[09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1
        https://git.kernel.org/arm64/c/0a648056d68d
[10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1
        https://git.kernel.org/arm64/c/1ecf3dcb1363
[11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1
        https://git.kernel.org/arm64/c/f4f5969e3542
[12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1
        https://git.kernel.org/arm64/c/d092106d7353
[13/38] arm64/sysreg: Standardise naming for MVFR0_EL1
        https://git.kernel.org/arm64/c/a3aab94801de
[14/38] arm64/sysreg: Standardise naming for MVFR1_EL1
        https://git.kernel.org/arm64/c/d3e1aa85b1b2
[15/38] arm64/sysreg: Standardise naming for MVFR2_EL1
        https://git.kernel.org/arm64/c/c6e155e8e561
[16/38] arm64/sysreg: Extend the maximum width of a register and symbol name
        https://git.kernel.org/arm64/c/7587cdef5592
[17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation
        https://git.kernel.org/arm64/c/8893df290e36
[18/38] arm64/sysreg: Convert ID_MMFR1_EL1 to automatic generation
        https://git.kernel.org/arm64/c/7e2f00bea3db
[19/38] arm64/sysreg: Convert ID_MMFR2_EL1 to automatic generation
        https://git.kernel.org/arm64/c/fbfba88b6ae1
[20/38] arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
        https://git.kernel.org/arm64/c/8fe2a9c578b0
[21/38] arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
        https://git.kernel.org/arm64/c/5b380ae0e2b3
[22/38] arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
        https://git.kernel.org/arm64/c/258a96b25a9d
[23/38] arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
        https://git.kernel.org/arm64/c/892386a6a807
[24/38] arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
        https://git.kernel.org/arm64/c/dfa70ae8d8c2
[25/38] arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
        https://git.kernel.org/arm64/c/d07016c96530
[26/38] arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
        https://git.kernel.org/arm64/c/849cc9bd9f0e
[27/38] arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
        https://git.kernel.org/arm64/c/f4e9ce12dd88
[28/38] arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
        https://git.kernel.org/arm64/c/5ea58a1b5c7a
[29/38] arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
        https://git.kernel.org/arm64/c/fb0b8d1a24d8
[30/38] arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
        https://git.kernel.org/arm64/c/1224308075f1
[31/38] arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
        https://git.kernel.org/arm64/c/039d372305ff
[32/38] arm64/sysreg: Convert MVFR0_EL1 to automatic generation
        https://git.kernel.org/arm64/c/e79c94a2a487
[33/38] arm64/sysreg: Convert MVFR1_EL1 to automatic generation
        https://git.kernel.org/arm64/c/c9b718eda706
[34/38] arm64/sysreg: Convert MVFR2_EL1 to automatic generation
        https://git.kernel.org/arm64/c/f70a810e01b2
[35/38] arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
        https://git.kernel.org/arm64/c/8a950efa1ff0
[36/38] arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
        https://git.kernel.org/arm64/c/58e010516ee6
[37/38] arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
        https://git.kernel.org/arm64/c/d044a9fbace7
[38/38] arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
        https://git.kernel.org/arm64/c/fa057722978e

Cheers,
Marc Zyngier Dec. 2, 2022, 3:52 p.m. UTC | #3 
On Fri, 02 Dec 2022 11:17:42 +0000,
Will Deacon <will@kernel.org> wrote:
> 
> [+Marc]
> 
> On Wed, 30 Nov 2022 17:15:59 +0000, James Morse wrote:
> > Changes since the v1
> >  * Duplicate definition muck up in patch 29 fixed.
> >  * Rebased onto arm64/for-next/sysregs, which is just rc4.
> > 
> 
> Applied to arm64 (for-next/sysregs), thanks!
> 
> Note that this conflicts with Marc's PMU rework in the kvmarm tree in
> slightly annoying ways (things like "IMP_DEF" => "IMPDEF"). I've had a
> crack at resolving that at the end of this email.

Thanks. I've done a merge and ended up with the same resolution, so
something must be vaguely correct.

The more annoying part is that the kvmarm/next branch is based on rc3,
while this drags rc4 into the mix, leading to a pretty ugly changelog.

I'll rebuild the branch next week with rc4 as the merge base, which
should be less awful.

Thanks,

	M.