| Message ID | 20221205002951.1788783-1-alison.schofield@intel.com |
|---|---|
| State | Accepted |
| Commit | 14628aec8415e4847ae7e470b175412896716cd8 |
| Headers | show |
| Series | cxl/acpi: Fail decoder add if CXIMS for HBIG is missing | expand |
On 12/4/2022 5:29 PM, alison.schofield@intel.com wrote: > From: Alison Schofield <alison.schofield@intel.com> > > The BIOS provided CXIMS (CXL XOR Interleave Math Structure) is required > for calculating a targets position in an interleave list during region > creation. The CXL driver expects to discover a CXIMS that matches the > HBIG (Host Bridge Interleave Granularity) and stores the xormaps found > in that CXIMS for retrieval during region creation. > > If there is no CXIMS for an HBIG, no maps are stored. That leads to a > NULL pointer dereference at xormap retrieval during region creation. > > Add a check during ACPI probe for the case of no matching CXIMS. Emit > an error message and fail to add the decoder. > > Fixes: f9db85bfec0d ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)") > Suggested-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > > Not sure the Commit-ID in Fixes tag will persist. (from cxl/pending) > > drivers/cxl/acpi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > index 657ef250d848..420e322c85a1 100644 > --- a/drivers/cxl/acpi.c > +++ b/drivers/cxl/acpi.c > @@ -282,6 +282,11 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, > cxl_parse_cxims, &cxims_ctx); > if (rc < 0) > goto err_xormap; > + if (!cxlrd->platform_data) { > + dev_err(dev, "No CXIMS for HBIG %u\n", ig); > + rc = -EINVAL; > + goto err_xormap; > + } > } > } > rc = cxl_decoder_add(cxld, target_map); > > base-commit: d72a5b810410c076d4dd63fe542a5a4d6c145cfa
alison.schofield@ wrote: > From: Alison Schofield <alison.schofield@intel.com> > > The BIOS provided CXIMS (CXL XOR Interleave Math Structure) is required > for calculating a targets position in an interleave list during region > creation. The CXL driver expects to discover a CXIMS that matches the > HBIG (Host Bridge Interleave Granularity) and stores the xormaps found > in that CXIMS for retrieval during region creation. > > If there is no CXIMS for an HBIG, no maps are stored. That leads to a > NULL pointer dereference at xormap retrieval during region creation. > > Add a check during ACPI probe for the case of no matching CXIMS. Emit > an error message and fail to add the decoder. > > Fixes: f9db85bfec0d ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)") > Suggested-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Alison Schofield <alison.schofield@intel.com> > --- > > Not sure the Commit-ID in Fixes tag will persist. (from cxl/pending) Looks good to me, and yes that commit-id is stable even with the recent rebase to fixup some authorship in the for-6.2/cxl-rch branch.
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 657ef250d848..420e322c85a1 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -282,6 +282,11 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, cxl_parse_cxims, &cxims_ctx); if (rc < 0) goto err_xormap; + if (!cxlrd->platform_data) { + dev_err(dev, "No CXIMS for HBIG %u\n", ig); + rc = -EINVAL; + goto err_xormap; + } } } rc = cxl_decoder_add(cxld, target_map);