| Message ID | 20221201015003.295769-2-kim.phillips@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/cpu, kvm: Support AMD Automatic IBRS | expand |
On Wed, Nov 30, 2022 at 07:49:57PM -0600, Kim Phillips wrote: > It's a part of the CPUID 0x80000021 leaf, and this allows us to ^^ Please use passive voice in your commit message: no "we" or "I", etc, and describe your changes in imperative mood. Personal pronouns are ambiguous in text, especially with so many parties/companies/etc developing the kernel so let's avoid them please. > group this and other CPUID 0x80000021 EAX feature bits to being > propagated via kvm_set_cpu_caps instead of open-coding them in > __do_cpuid_func(). > > Signed-off-by: Kim Phillips <kim.phillips@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 11a0e06362e4..b16fdcedc2b5 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -307,6 +307,7 @@ > #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */ > #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ > #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ > +#define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ Right, what is the use of this bit in a KVM guest? Running perf tool in a guest would use that bit how? Thx.
On 12/5/22 4:23 AM, Borislav Petkov wrote: > On Wed, Nov 30, 2022 at 07:49:57PM -0600, Kim Phillips wrote: >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -307,6 +307,7 @@ >> #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */ >> #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ >> #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ >> +#define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ > > Right, what is the use of this bit in a KVM guest? Running perf tool in > a guest would use that bit how? This is starting to get off-topic. Propagating that bit to the guest was originally added by: commit 58b3d12c0a860cda34ed9d2378078ea5134e6812 Author: Paolo Bonzini <pbonzini@redhat.com> Date: Thu Oct 28 13:26:38 2021 -0400 KVM: x86: add support for CPUID leaf 0x80000021 In the future, it will be used by: https://lore.kernel.org/lkml/20221201021948.9259-1-aik@amd.com/ to allow hardware swapping of debug registers. If it can't be used in the nested VM case, I can remove the guest propagation code for it from PATCH 4/7 with a Fixes: for the above commit, but this 1/7 PATCH will remain. Thanks, Kim
On Mon, Dec 05, 2022 at 11:32:01AM -0600, Kim Phillips wrote:
> This is starting to get off-topic.
What does that mean?
Are you saying I'm not allowed to ask why stuff is added?
On 12/5/22 2:20 PM, Borislav Petkov wrote: > On Mon, Dec 05, 2022 at 11:32:01AM -0600, Kim Phillips wrote: >> This is starting to get off-topic. > > What does that mean? > > Are you saying I'm not allowed to ask why stuff is added? No, sorry. You had asked "what is the use of this bit in a KVM guest?", and I'm saying that it was already being propagated to the guest prior to this patchseries, which is about propagating the Automatic IBRS feature. That's all. Thanks, Kim
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 11a0e06362e4..b16fdcedc2b5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -307,6 +307,7 @@ #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */ #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ +#define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index f53944fb8f7f..079e253e1049 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 }
It's a part of the CPUID 0x80000021 leaf, and this allows us to group this and other CPUID 0x80000021 EAX feature bits to being propagated via kvm_set_cpu_caps instead of open-coding them in __do_cpuid_func(). Signed-off-by: Kim Phillips <kim.phillips@amd.com> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+)