| Message ID | 20221207100335.290481-14-bmeng@tinylab.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC | expand |
On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote: > At present the SiFive PLIC model "priority-base" expects interrupt > priority register base starting from source 1 instead source 0, > that's why on most platforms "priority-base" is set to 0x04 except > 'opentitan' machine. 'opentitan' should have set "priority-base" > to 0x04 too. > > Note the irq number calculation in sifive_plic_{read,write} is > correct as the codes make up for the irq number by adding 1. > > Let's simply update "priority-base" to start from interrupt source > 0 and add a comment to make it crystal clear. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Wilfred > --- > > (no changes since v1) > > include/hw/riscv/microchip_pfsoc.h | 2 +- > include/hw/riscv/shakti_c.h | 2 +- > include/hw/riscv/sifive_e.h | 2 +- > include/hw/riscv/sifive_u.h | 2 +- > include/hw/riscv/virt.h | 2 +- > hw/intc/sifive_plic.c | 5 +++-- > 6 files changed, 8 insertions(+), 7 deletions(-) > > diff --git a/include/hw/riscv/microchip_pfsoc.h > b/include/hw/riscv/microchip_pfsoc.h > index 577efad0c4..e65ffeb02d 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -155,7 +155,7 @@ enum { > > #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 > #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 > -#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 > +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00 > #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 > #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 > #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 > diff --git a/include/hw/riscv/shakti_c.h > b/include/hw/riscv/shakti_c.h > index daf0aae13f..539fe1156d 100644 > --- a/include/hw/riscv/shakti_c.h > +++ b/include/hw/riscv/shakti_c.h > @@ -65,7 +65,7 @@ enum { > #define SHAKTI_C_PLIC_NUM_SOURCES 28 > /* Excluding Priority 0 */ > #define SHAKTI_C_PLIC_NUM_PRIORITIES 2 > -#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04 > +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00 > #define SHAKTI_C_PLIC_PENDING_BASE 0x1000 > #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 > #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 > diff --git a/include/hw/riscv/sifive_e.h > b/include/hw/riscv/sifive_e.h > index 9e58247fd8..b824a79e2d 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -89,7 +89,7 @@ enum { > */ > #define SIFIVE_E_PLIC_NUM_SOURCES 53 > #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 > -#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 > +#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00 > #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 > #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 > #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 > diff --git a/include/hw/riscv/sifive_u.h > b/include/hw/riscv/sifive_u.h > index 8f63a183c4..e680d61ece 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -158,7 +158,7 @@ enum { > > #define SIFIVE_U_PLIC_NUM_SOURCES 54 > #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 > -#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 > +#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00 > #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 > #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 > #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index e1ce0048af..3407c9e8dd 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -98,7 +98,7 @@ enum { > #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 > #define VIRT_IRQCHIP_MAX_GUESTS ((1U << > VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) > > -#define VIRT_PLIC_PRIORITY_BASE 0x04 > +#define VIRT_PLIC_PRIORITY_BASE 0x00 > #define VIRT_PLIC_PENDING_BASE 0x1000 > #define VIRT_PLIC_ENABLE_BASE 0x2000 > #define VIRT_PLIC_ENABLE_STRIDE 0x80 > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c > index 1edeb1e1ed..1a792cc3f5 100644 > --- a/hw/intc/sifive_plic.c > +++ b/hw/intc/sifive_plic.c > @@ -140,7 +140,7 @@ static uint64_t sifive_plic_read(void *opaque, > hwaddr addr, unsigned size) > SiFivePLICState *plic = opaque; > > if (addr_between(addr, plic->priority_base, plic->num_sources << > 2)) { > - uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; > + uint32_t irq = (addr - plic->priority_base) >> 2; > > return plic->source_priority[irq]; > } else if (addr_between(addr, plic->pending_base, plic- > >num_sources >> 3)) { > @@ -187,7 +187,7 @@ static void sifive_plic_write(void *opaque, > hwaddr addr, uint64_t value, > SiFivePLICState *plic = opaque; > > if (addr_between(addr, plic->priority_base, plic->num_sources << > 2)) { > - uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; > + uint32_t irq = (addr - plic->priority_base) >> 2; > > if (((plic->num_priorities + 1) & plic->num_priorities) == > 0) { > /* > @@ -428,6 +428,7 @@ static Property sifive_plic_properties[] = { > /* number of interrupt sources including interrupt source 0 */ > DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, > 1), > DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, > num_priorities, 0), > + /* interrupt priority register base starting from source 0 */ > DEFINE_PROP_UINT32("priority-base", SiFivePLICState, > priority_base, 0), > DEFINE_PROP_UINT32("pending-base", SiFivePLICState, > pending_base, 0), > DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, > 0),
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 577efad0c4..e65ffeb02d 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -155,7 +155,7 @@ enum { #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 -#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index daf0aae13f..539fe1156d 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -65,7 +65,7 @@ enum { #define SHAKTI_C_PLIC_NUM_SOURCES 28 /* Excluding Priority 0 */ #define SHAKTI_C_PLIC_NUM_PRIORITIES 2 -#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04 +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00 #define SHAKTI_C_PLIC_PENDING_BASE 0x1000 #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 9e58247fd8..b824a79e2d 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -89,7 +89,7 @@ enum { */ #define SIFIVE_E_PLIC_NUM_SOURCES 53 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 -#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 +#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 8f63a183c4..e680d61ece 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -158,7 +158,7 @@ enum { #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 -#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 +#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e1ce0048af..3407c9e8dd 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -98,7 +98,7 @@ enum { #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) -#define VIRT_PLIC_PRIORITY_BASE 0x04 +#define VIRT_PLIC_PRIORITY_BASE 0x00 #define VIRT_PLIC_PENDING_BASE 0x1000 #define VIRT_PLIC_ENABLE_BASE 0x2000 #define VIRT_PLIC_ENABLE_STRIDE 0x80 diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 1edeb1e1ed..1a792cc3f5 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -140,7 +140,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) SiFivePLICState *plic = opaque; if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { - uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; + uint32_t irq = (addr - plic->priority_base) >> 2; return plic->source_priority[irq]; } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) { @@ -187,7 +187,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, SiFivePLICState *plic = opaque; if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { - uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; + uint32_t irq = (addr - plic->priority_base) >> 2; if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { /* @@ -428,6 +428,7 @@ static Property sifive_plic_properties[] = { /* number of interrupt sources including interrupt source 0 */ DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1), DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0), + /* interrupt priority register base starting from source 0 */ DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0), DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note the irq number calculation in sifive_plic_{read,write} is correct as the codes make up for the irq number by adding 1. Let's simply update "priority-base" to start from interrupt source 0 and add a comment to make it crystal clear. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- (no changes since v1) include/hw/riscv/microchip_pfsoc.h | 2 +- include/hw/riscv/shakti_c.h | 2 +- include/hw/riscv/sifive_e.h | 2 +- include/hw/riscv/sifive_u.h | 2 +- include/hw/riscv/virt.h | 2 +- hw/intc/sifive_plic.c | 5 +++-- 6 files changed, 8 insertions(+), 7 deletions(-)