| Message ID | 20221212122058.597-1-quic_shazhuss@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] arm64: dts: qcom: sa8540p-ride: enable pcie2a node | expand |
On Mon, Dec 12, 2022 at 05:50:59PM +0530, Shazad Hussain wrote: > Add the pcie2a, pcie2a_phy, and respective tlmm > nodes that are needed to get pcie 2a controller > enabled on Qdrive3. > > This patch enables 4GB 64bit memory space for > PCIE_2A to have BAR allocations of 64bit pref mem > needed on this Qdrive3 platform with dual SoCs > for root port and switch NT-EP. Hence this ranges > property is overridden in sa8540p-ride.dts only. > > Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > --- > Changes since v1: > - Fix ranges property indentation (Konrad) > > This patch depends on below patch series for vreg_l11a. > > [v4] arm64: dts: qcom: sa8540p-ride: enable PCIe support > https://lore.kernel.org/all/20221206161916.315640-1-bmasney@redhat.com/ I verified that this matches what's in downstream. Reviewed-by: Brian Masney <bmasney@redhat.com> I'm not able to test this yet since we're still on an old version of the PCIe switch firmware and I need to get that upgraded first. Note that your patch won't apply to linux-next since the v3 of my pcie3a patch is what was actually merged into the qcom tree. Can you resend? You can move the tlmm node to the bottom and add the PINCTRL comment. I have some i2c and SPI changes that I'll be posting soon where I already made that change but I'll hold off for you to post a new version and base on top of yours. Brian
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index bb4afd3a9632..7ce104fea4f8 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -146,6 +146,27 @@ vreg_l8g: ldo8 { }; }; +&pcie2a { + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, + <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + &pcie3a { ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, @@ -247,6 +268,29 @@ &xo_board_clk { /* PINCTRL */ &tlmm { + pcie2a_default: pcie2a-default-state { + perst-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie3a_default: pcie3a-default-state { perst-pins { pins = "gpio151";
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to get pcie 2a controller enabled on Qdrive3. This patch enables 4GB 64bit memory space for PCIE_2A to have BAR allocations of 64bit pref mem needed on this Qdrive3 platform with dual SoCs for root port and switch NT-EP. Hence this ranges property is overridden in sa8540p-ride.dts only. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> --- Changes since v1: - Fix ranges property indentation (Konrad) This patch depends on below patch series for vreg_l11a. [v4] arm64: dts: qcom: sa8540p-ride: enable PCIe support https://lore.kernel.org/all/20221206161916.315640-1-bmasney@redhat.com/ arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+)