| Message ID | 20221213160112.1900410-4-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells | expand |
Am Dienstag, dem 13.12.2022 um 17:01 +0100 schrieb Lucas Stach: > Expose the high performance PLL as a regular Linux clock, so the > PCIe PHY can use it when there is no external refclock provided. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/soc/imx/imx8mp-blk-ctrl.c | 99 +++++++++++++++++++++++++++++++ > 1 file changed, 99 insertions(+) > > diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c > index b3d9f6e083ba..ad5aebd640eb 100644 > --- a/drivers/soc/imx/imx8mp-blk-ctrl.c > +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c > @@ -5,6 +5,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/clk-provider.h> > #include <linux/device.h> > #include <linux/interconnect.h> > #include <linux/module.h> > @@ -21,6 +22,15 @@ > #define USB_CLOCK_MODULE_EN BIT(1) > #define PCIE_PHY_APB_RST BIT(4) > #define PCIE_PHY_INIT_RST BIT(5) > +#define GPR_REG1 0x4 > +#define PLL_LOCK BIT(13) > +#define GPR_REG2 0x8 > +#define P_PLL_MASK GENMASK(5, 0) > +#define M_PLL_MASK GENMASK(15, 6) > +#define S_PLL_MASK GENMASK(18, 16) > +#define GPR_REG3 0xc > +#define PLL_CKE BIT(17) > +#define PLL_RST BIT(31) > > struct imx8mp_blk_ctrl_domain; > > @@ -74,6 +84,94 @@ to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd) > return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd); > } > > +struct clk_hsio_pll { > + struct clk_hw hw; > + struct regmap *regmap; > +}; > + > +static inline struct clk_hsio_pll *to_clk_hsio_pll(struct clk_hw *hw) > +{ > + return container_of(hw, struct clk_hsio_pll, hw); > +} > + > +static int clk_hsio_pll_prepare(struct clk_hw *hw) > +{ > + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); > + u32 val; > + > + /* set the PLL configuration */ > + regmap_update_bits(clk->regmap, GPR_REG2, > + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK, > + FIELD_PREP(P_PLL_MASK, 12) | > + FIELD_PREP(M_PLL_MASK, 800) | > + FIELD_PREP(S_PLL_MASK, 4)); > + > + /* de-assert PLL reset */ > + regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); > + > + /* enable PLL */ > + regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); > + > + return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, > + val & PLL_LOCK, 10, 100); > +} > + > +static void clk_hsio_pll_unprepare(struct clk_hw *hw) > +{ > + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); > + > + regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); > +} > + > +static int clk_hsio_pll_is_prepared(struct clk_hw *hw) > +{ > + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); > + > + return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); > +} > + > +static unsigned long clk_hsio_pll_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + return 100000000; > +} > + > +static const struct clk_ops clk_hsio_pll_ops = { > + .prepare = clk_hsio_pll_prepare, > + .unprepare = clk_hsio_pll_unprepare, > + .is_prepared = clk_hsio_pll_is_prepared, > + .recalc_rate = clk_hsio_pll_recalc_rate, > +}; > + > +int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc) > +{ > + struct clk_hsio_pll *clk_hsio_pll; > + struct clk_hw *hw; > + struct clk_init_data init = {}; > + int ret; > + > + printk("%s\n", __func__); This printk should obviously not be here. Removed locally. I'll wait for some feedback before sending v2. Regards, Lucas > + > + clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL); > + if (!clk_hsio_pll) > + return -ENOMEM; > + > + init.name = "hsio_pll"; > + init.ops = &clk_hsio_pll_ops; > + init.parent_names = (const char *[]){"osc_24m"}; > + init.num_parents = 1; > + > + clk_hsio_pll->regmap = bc->regmap; > + clk_hsio_pll->hw.init = &init; > + > + hw = &clk_hsio_pll->hw; > + ret = devm_clk_hw_register(bc->dev, hw); > + if (ret) > + return ret; > + > + return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw); > +} > + > static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, > struct imx8mp_blk_ctrl_domain *domain) > { > @@ -188,6 +286,7 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = { > > static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = { > .max_reg = 0x24, > + .probe = imx8mp_hsio_blk_ctrl_probe, > .power_on = imx8mp_hsio_blk_ctrl_power_on, > .power_off = imx8mp_hsio_blk_ctrl_power_off, > .power_notifier_fn = imx8mp_hsio_power_notifier,
On Wed, 2022-12-14 at 04:40 +0800, kernel test robot wrote: > Hi Lucas, > > I love your patch! Perhaps something to improve: > > [auto build test WARNING on robh/for-next] > [also build test WARNING on shawnguo/for-next krzk/for-next krzk-dt/for-next linus/master v6.1 next-20221213] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: > https://github.com/intel-lab-lkp/linux/commits/Lucas-Stach/dt-bindings-soc-imx8mp-hsio-blk-ctrl-add-clock-cells/20221214-000245 > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next > patch link: https://lore.kernel.org/r/20221213160112.1900410-4-l.stach%40pengutronix.de > patch subject: [PATCH 4/4] soc: imx: imx8mp-blk-ctrl: expose high performance PLL clock > config: m68k-allyesconfig Yeah, our Gitlab CI gave me the same even for e.g. imx_v6_v7_defconfig: drivers/soc/imx/imx8mp-blk-ctrl.c: In function 'clk_hsio_pll_prepare': 1765drivers/soc/imx/imx8mp-blk-ctrl.c:105:7: error: implicit declaration of function 'FIELD_PREP' [- Werror=implicit-function-declaration] 1766 105 | FIELD_PREP(P_PLL_MASK, 12) | 1767 | ^~~~~~~~~~ > compiler: m68k-linux-gcc (GCC) 12.1.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/intel-lab-lkp/linux/commit/5046774c03a3496c19069b9237fee85273c215aa > git remote add linux-review https://github.com/intel-lab-lkp/linux > git fetch --no-tags linux-review Lucas-Stach/dt-bindings-soc-imx8mp-hsio-blk-ctrl-add-clock- > cells/20221214-000245 > git checkout 5046774c03a3496c19069b9237fee85273c215aa > # save the config file > mkdir build_dir && cp config build_dir/.config > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k > SHELL=/bin/bash drivers/soc/ > > If you fix the issue, kindly add following tag where applicable > > Reported-by: kernel test robot <lkp@intel.com> > > All warnings (new ones prefixed by >>): > > drivers/soc/imx/imx8mp-blk-ctrl.c: In function 'clk_hsio_pll_prepare': > drivers/soc/imx/imx8mp-blk-ctrl.c:105:28: error: implicit declaration of function 'FIELD_PREP' [- > Werror=implicit-function-declaration] > 105 | FIELD_PREP(P_PLL_MASK, 12) | > | ^~~~~~~~~~ > drivers/soc/imx/imx8mp-blk-ctrl.c: At top level: > > > drivers/soc/imx/imx8mp-blk-ctrl.c:146:5: warning: no previous prototype for 'imx8mp_hsio_blk_ctrl_probe' > > > [-Wmissing-prototypes] > 146 | int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc) > | ^~~~~~~~~~~~~~~~~~~~~~~~~~ > cc1: some warnings being treated as errors > > > vim +/imx8mp_hsio_blk_ctrl_probe +146 drivers/soc/imx/imx8mp-blk-ctrl.c > > 145 > > 146 int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc) > 147 { > 148 struct clk_hsio_pll *clk_hsio_pll; > 149 struct clk_hw *hw; > 150 struct clk_init_data init = {}; > 151 int ret; > 152 > 153 printk("%s\n", __func__); > 154 > 155 clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL); > 156 if (!clk_hsio_pll) > 157 return -ENOMEM; > 158 > 159 init.name = "hsio_pll"; > 160 init.ops = &clk_hsio_pll_ops; > 161 init.parent_names = (const char *[]){"osc_24m"}; > 162 init.num_parents = 1; > 163 > 164 clk_hsio_pll->regmap = bc->regmap; > 165 clk_hsio_pll->hw.init = &init; > 166 > 167 hw = &clk_hsio_pll->hw; > 168 ret = devm_clk_hw_register(bc->dev, hw); > 169 if (ret) > 170 return ret; > 171 > 172 return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw); > 173 } > 174
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index b3d9f6e083ba..ad5aebd640eb 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -5,6 +5,7 @@ */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/device.h> #include <linux/interconnect.h> #include <linux/module.h> @@ -21,6 +22,15 @@ #define USB_CLOCK_MODULE_EN BIT(1) #define PCIE_PHY_APB_RST BIT(4) #define PCIE_PHY_INIT_RST BIT(5) +#define GPR_REG1 0x4 +#define PLL_LOCK BIT(13) +#define GPR_REG2 0x8 +#define P_PLL_MASK GENMASK(5, 0) +#define M_PLL_MASK GENMASK(15, 6) +#define S_PLL_MASK GENMASK(18, 16) +#define GPR_REG3 0xc +#define PLL_CKE BIT(17) +#define PLL_RST BIT(31) struct imx8mp_blk_ctrl_domain; @@ -74,6 +84,94 @@ to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd) return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd); } +struct clk_hsio_pll { + struct clk_hw hw; + struct regmap *regmap; +}; + +static inline struct clk_hsio_pll *to_clk_hsio_pll(struct clk_hw *hw) +{ + return container_of(hw, struct clk_hsio_pll, hw); +} + +static int clk_hsio_pll_prepare(struct clk_hw *hw) +{ + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); + u32 val; + + /* set the PLL configuration */ + regmap_update_bits(clk->regmap, GPR_REG2, + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK, + FIELD_PREP(P_PLL_MASK, 12) | + FIELD_PREP(M_PLL_MASK, 800) | + FIELD_PREP(S_PLL_MASK, 4)); + + /* de-assert PLL reset */ + regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); + + /* enable PLL */ + regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); + + return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, + val & PLL_LOCK, 10, 100); +} + +static void clk_hsio_pll_unprepare(struct clk_hw *hw) +{ + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); + + regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); +} + +static int clk_hsio_pll_is_prepared(struct clk_hw *hw) +{ + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); + + return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); +} + +static unsigned long clk_hsio_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 100000000; +} + +static const struct clk_ops clk_hsio_pll_ops = { + .prepare = clk_hsio_pll_prepare, + .unprepare = clk_hsio_pll_unprepare, + .is_prepared = clk_hsio_pll_is_prepared, + .recalc_rate = clk_hsio_pll_recalc_rate, +}; + +int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc) +{ + struct clk_hsio_pll *clk_hsio_pll; + struct clk_hw *hw; + struct clk_init_data init = {}; + int ret; + + printk("%s\n", __func__); + + clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL); + if (!clk_hsio_pll) + return -ENOMEM; + + init.name = "hsio_pll"; + init.ops = &clk_hsio_pll_ops; + init.parent_names = (const char *[]){"osc_24m"}; + init.num_parents = 1; + + clk_hsio_pll->regmap = bc->regmap; + clk_hsio_pll->hw.init = &init; + + hw = &clk_hsio_pll->hw; + ret = devm_clk_hw_register(bc->dev, hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw); +} + static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain) { @@ -188,6 +286,7 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = { static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = { .max_reg = 0x24, + .probe = imx8mp_hsio_blk_ctrl_probe, .power_on = imx8mp_hsio_blk_ctrl_power_on, .power_off = imx8mp_hsio_blk_ctrl_power_off, .power_notifier_fn = imx8mp_hsio_power_notifier,
Expose the high performance PLL as a regular Linux clock, so the PCIe PHY can use it when there is no external refclock provided. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/soc/imx/imx8mp-blk-ctrl.c | 99 +++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+)