| Message ID | 1670967848-31475-6-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add data-lanes and link-frequencies to dp_out endpoint | expand |
On 13 December 2022 23:44:08 EET, Kuogee Hsieh <quic_khsieh@quicinc.com> wrote: >By default, HBR2 (5.4G) is the max link link be supported. This patch uses the >actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. >Supporting HBR3 is a consequence of that. > >Changes in v2: >-- add max link rate from dtsi > >Changes in v3: >-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint > >Changes in v4: >-- delete unnecessary pr_err > >Changes in v5: >-- split parser function into different patch > >Changes in v9: >-- revised commit test > >Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >--- > drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ > drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- > drivers/gpu/drm/msm/dp/dp_panel.h | 1 + > 3 files changed, 9 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >index bfd0aef..edee550 100644 >--- a/drivers/gpu/drm/msm/dp/dp_display.c >+++ b/drivers/gpu/drm/msm/dp/dp_display.c >@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) > struct edid *edid; > > dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; >+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; >+ >+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", >+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); > > rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); > if (rc) >diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c >index 5149ceb..933fa9c 100644 >--- a/drivers/gpu/drm/msm/dp/dp_panel.c >+++ b/drivers/gpu/drm/msm/dp/dp_panel.c >@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) > link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); > link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; > >+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */ Nit: property. And below too. > if (link_info->num_lanes > dp_panel->max_dp_lanes) > link_info->num_lanes = dp_panel->max_dp_lanes; > >- /* Limit support upto HBR2 until HBR3 support is added */ >- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) >- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); >+ /* Limit link rate from link-frequencies of endpoint properity of dtsi */ >+ if (link_info->rate > dp_panel->max_dp_link_rate) >+ link_info->rate = dp_panel->max_dp_link_rate; > > drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); > drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); >diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h >index d861197a..f04d021 100644 >--- a/drivers/gpu/drm/msm/dp/dp_panel.h >+++ b/drivers/gpu/drm/msm/dp/dp_panel.h >@@ -50,6 +50,7 @@ struct dp_panel { > > u32 vic; > u32 max_dp_lanes; >+ u32 max_dp_link_rate; > > u32 max_bw_code; > };
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index bfd0aef..edee550 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) struct edid *edid; dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; + dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; + + drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", + dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5149ceb..933fa9c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; + /* Limit data lanes from data-lanes of endpoint properity of dtsi */ if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes = dp_panel->max_dp_lanes; - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); + /* Limit link rate from link-frequencies of endpoint properity of dtsi */ + if (link_info->rate > dp_panel->max_dp_link_rate) + link_info->rate = dp_panel->max_dp_link_rate; drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index d861197a..f04d021 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct dp_panel { u32 vic; u32 max_dp_lanes; + u32 max_dp_link_rate; u32 max_bw_code; };