| Message ID | 20220503095127.48710-4-eugen.hristev@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: atmel: atmel-isc: implement media controller | expand |
On 5/3/22 12:51, Eugen Hristev wrote: > Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC > (csi2 demux controller). > These nodes represent the top level of the video capture hardware pipeline > and are directly connected in hardware. > > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> > --- > Changes in v10: > - nodes disabled by default > > arch/arm/boot/dts/sama7g5.dtsi | 51 ++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi > index 4decd3a91a76..fe9c6df9819b 100644 > --- a/arch/arm/boot/dts/sama7g5.dtsi > +++ b/arch/arm/boot/dts/sama7g5.dtsi > @@ -454,6 +454,57 @@ sdmmc2: mmc@e120c000 { > status = "disabled"; > }; > > + csi2dc: csi2dc@e1404000 { > + compatible = "microchip,sama7g5-csi2dc"; > + reg = <0xe1404000 0x500>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; > + clock-names = "pclk", "scck"; > + assigned-clocks = <&xisc>; > + assigned-clock-rates = <266000000>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + csi2dc_in: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + csi2dc_out: endpoint { > + bus-width = <14>; > + hsync-active = <1>; > + vsync-active = <1>; > + remote-endpoint = <&xisc_in>; > + }; > + }; > + }; > + }; > + > + xisc: xisc@e1408000 { > + compatible = "microchip,sama7g5-isc"; > + reg = <0xe1408000 0x2000>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; > + clock-names = "hclock"; > + #clock-cells = <0>; > + clock-output-names = "isc-mck"; > + status = "disabled"; > + > + port { > + xisc_in: endpoint { > + bus-type = <5>; /* Parallel */ > + bus-width = <14>; > + hsync-active = <1>; > + vsync-active = <1>; > + remote-endpoint = <&csi2dc_out>; > + }; > + }; > + }; > + > pwm: pwm@e1604000 { > compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; > reg = <0xe1604000 0x4000>; Hello Claudiu, Nicolas, This patch is ready to go now , as the media controller support for XISC driver is in tree. Let me know if you need this to be resent. Thanks, Eugen
On 14.12.2022 14:55, Eugen Hristev - M18282 wrote: > On 5/3/22 12:51, Eugen Hristev wrote: >> Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC >> (csi2 demux controller). >> These nodes represent the top level of the video capture hardware pipeline >> and are directly connected in hardware. >> >> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> >> --- >> Changes in v10: >> - nodes disabled by default >> >> arch/arm/boot/dts/sama7g5.dtsi | 51 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi >> index 4decd3a91a76..fe9c6df9819b 100644 >> --- a/arch/arm/boot/dts/sama7g5.dtsi >> +++ b/arch/arm/boot/dts/sama7g5.dtsi >> @@ -454,6 +454,57 @@ sdmmc2: mmc@e120c000 { >> status = "disabled"; >> }; >> >> + csi2dc: csi2dc@e1404000 { >> + compatible = "microchip,sama7g5-csi2dc"; >> + reg = <0xe1404000 0x500>; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; >> + clock-names = "pclk", "scck"; >> + assigned-clocks = <&xisc>; >> + assigned-clock-rates = <266000000>; >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + port@0 { >> + reg = <0>; >> + csi2dc_in: endpoint { >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + csi2dc_out: endpoint { >> + bus-width = <14>; >> + hsync-active = <1>; >> + vsync-active = <1>; >> + remote-endpoint = <&xisc_in>; >> + }; >> + }; >> + }; >> + }; >> + >> + xisc: xisc@e1408000 { >> + compatible = "microchip,sama7g5-isc"; >> + reg = <0xe1408000 0x2000>; >> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; >> + clock-names = "hclock"; >> + #clock-cells = <0>; >> + clock-output-names = "isc-mck"; >> + status = "disabled"; >> + >> + port { >> + xisc_in: endpoint { >> + bus-type = <5>; /* Parallel */ >> + bus-width = <14>; >> + hsync-active = <1>; >> + vsync-active = <1>; >> + remote-endpoint = <&csi2dc_out>; >> + }; >> + }; >> + }; >> + >> pwm: pwm@e1604000 { >> compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; >> reg = <0xe1604000 0x4000>; > > Hello Claudiu, Nicolas, Hi, Eugen, > > This patch is ready to go now , as the media controller support for XISC > driver is in tree. > > Let me know if you need this to be resent. No need. I'll take this one for the next PR. Thank you, Claudiu Beznea > > Thanks, > Eugen >
On 03.05.2022 12:51, Eugen Hristev wrote: > Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC > (csi2 demux controller). > These nodes represent the top level of the video capture hardware pipeline > and are directly connected in hardware. > > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Applied to at91-dt, thanks! > --- > Changes in v10: > - nodes disabled by default > > arch/arm/boot/dts/sama7g5.dtsi | 51 ++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi > index 4decd3a91a76..fe9c6df9819b 100644 > --- a/arch/arm/boot/dts/sama7g5.dtsi > +++ b/arch/arm/boot/dts/sama7g5.dtsi > @@ -454,6 +454,57 @@ sdmmc2: mmc@e120c000 { > status = "disabled"; > }; > > + csi2dc: csi2dc@e1404000 { > + compatible = "microchip,sama7g5-csi2dc"; > + reg = <0xe1404000 0x500>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; > + clock-names = "pclk", "scck"; > + assigned-clocks = <&xisc>; > + assigned-clock-rates = <266000000>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + csi2dc_in: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + csi2dc_out: endpoint { > + bus-width = <14>; > + hsync-active = <1>; > + vsync-active = <1>; > + remote-endpoint = <&xisc_in>; > + }; > + }; > + }; > + }; > + > + xisc: xisc@e1408000 { > + compatible = "microchip,sama7g5-isc"; > + reg = <0xe1408000 0x2000>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; > + clock-names = "hclock"; > + #clock-cells = <0>; > + clock-output-names = "isc-mck"; > + status = "disabled"; > + > + port { > + xisc_in: endpoint { > + bus-type = <5>; /* Parallel */ > + bus-width = <14>; > + hsync-active = <1>; > + vsync-active = <1>; > + remote-endpoint = <&csi2dc_out>; > + }; > + }; > + }; > + > pwm: pwm@e1604000 { > compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; > reg = <0xe1604000 0x4000>;
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 4decd3a91a76..fe9c6df9819b 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -454,6 +454,57 @@ sdmmc2: mmc@e120c000 { status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + status = "disabled"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>;
Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC (csi2 demux controller). These nodes represent the top level of the video capture hardware pipeline and are directly connected in hardware. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> --- Changes in v10: - nodes disabled by default arch/arm/boot/dts/sama7g5.dtsi | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)