| Message ID | 20221214075439.402485-1-andrzej.hajda@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: fix TLB invalidation for Gen12.50 video and compute engines | expand |
Hi Andrzej, On Wed, Dec 14, 2022 at 08:54:39AM +0100, Andrzej Hajda wrote: > In case of Gen12.50 video and compute engines, TLB_INV registers are > masked - to modify one bit, corresponding bit in upper half of the register > must be enabled, otherwise nothing happens. > > Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers") > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> > --- > Hi, > > This patch was sent already to ML, but together with refactoring patch. > Since it contains fix and should be merged ASAP it is sent separately > to get CI test results. to be scrupulous I'll wait for the full CI run and then I will push it Thanks, Andi > Regards > Andrzej > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 63f95c5f36146b..7eeee5a7cb33cb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -1100,9 +1100,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) > continue; > > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > + u32 val = BIT(engine->instance); > + > + if (engine->class == VIDEO_DECODE_CLASS || > + engine->class == VIDEO_ENHANCEMENT_CLASS || > + engine->class == COMPUTE_CLASS) > + val = _MASKED_BIT_ENABLE(val); > intel_gt_mcr_multicast_write_fw(gt, > xehp_regs[engine->class], > - BIT(engine->instance)); > + val); > } else { > rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > if (!i915_mmio_reg_offset(rb.reg)) > -- > 2.34.1
On Wed, Dec 14, 2022 at 08:54:39AM +0100, Andrzej Hajda wrote: > In case of Gen12.50 video and compute engines, TLB_INV registers are > masked - to modify one bit, corresponding bit in upper half of the register > must be enabled, otherwise nothing happens. > > Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers") > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Pushed to drm-intel-gt-next. Thanks, Andi > --- > Hi, > > This patch was sent already to ML, but together with refactoring patch. > Since it contains fix and should be merged ASAP it is sent separately > to get CI test results. > > Regards > Andrzej > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 63f95c5f36146b..7eeee5a7cb33cb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -1100,9 +1100,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) > continue; > > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > + u32 val = BIT(engine->instance); > + > + if (engine->class == VIDEO_DECODE_CLASS || > + engine->class == VIDEO_ENHANCEMENT_CLASS || > + engine->class == COMPUTE_CLASS) > + val = _MASKED_BIT_ENABLE(val); > intel_gt_mcr_multicast_write_fw(gt, > xehp_regs[engine->class], > - BIT(engine->instance)); > + val); > } else { > rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > if (!i915_mmio_reg_offset(rb.reg)) > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 63f95c5f36146b..7eeee5a7cb33cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1100,9 +1100,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) continue; if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { + u32 val = BIT(engine->instance); + + if (engine->class == VIDEO_DECODE_CLASS || + engine->class == VIDEO_ENHANCEMENT_CLASS || + engine->class == COMPUTE_CLASS) + val = _MASKED_BIT_ENABLE(val); intel_gt_mcr_multicast_write_fw(gt, xehp_regs[engine->class], - BIT(engine->instance)); + val); } else { rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); if (!i915_mmio_reg_offset(rb.reg))
In case of Gen12.50 video and compute engines, TLB_INV registers are masked - to modify one bit, corresponding bit in upper half of the register must be enabled, otherwise nothing happens. Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers") Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- Hi, This patch was sent already to ML, but together with refactoring patch. Since it contains fix and should be merged ASAP it is sent separately to get CI test results. Regards Andrzej --- drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)