| Message ID | 20221215154824.84198-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 41a37d157a613444c97e8f71a5fb2a21116b70d7 |
| Headers | show |
| Series | arm64: dts: qcom: qcs404: use symbol names for PCIe resets | expand |
On 15.12.2022 16:48, Dmitry Baryshkov wrote: > The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names > for PCIe resets, but it did not change the existing qcs404.dtsi to use > these names. Do it now and use symbol names to make it easier to check > and modify the dtsi in future. > > Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index a5324eecb50a..502dd6db491e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -806,7 +806,7 @@ pcie_phy: phy@7786000 { > > clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; > resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, > - <&gcc 21>; > + <&gcc GCC_PCIE_0_PIPE_ARES>; > reset-names = "phy", "pipe"; > > clock-output-names = "pcie_0_pipe_clk"; > @@ -1336,12 +1336,12 @@ pcie: pci@10000000 { > <&gcc GCC_PCIE_0_SLV_AXI_CLK>; > clock-names = "iface", "aux", "master_bus", "slave_bus"; > > - resets = <&gcc 18>, > - <&gcc 17>, > - <&gcc 15>, > - <&gcc 19>, > + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, > + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, > + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, > + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, > <&gcc GCC_PCIE_0_BCR>, > - <&gcc 16>; > + <&gcc GCC_PCIE_0_AHB_ARES>; > reset-names = "axi_m", > "axi_s", > "axi_m_sticky",
On Thu, 15 Dec 2022 17:48:24 +0200, Dmitry Baryshkov wrote: > The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names > for PCIe resets, but it did not change the existing qcs404.dtsi to use > these names. Do it now and use symbol names to make it easier to check > and modify the dtsi in future. > > Applied, thanks! [1/1] arm64: dts: qcom: qcs404: use symbol names for PCIe resets commit: 41a37d157a613444c97e8f71a5fb2a21116b70d7 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..502dd6db491e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -806,7 +806,7 @@ pcie_phy: phy@7786000 { clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; @@ -1336,12 +1336,12 @@ pcie: pci@10000000 { <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky",
The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names for PCIe resets, but it did not change the existing qcs404.dtsi to use these names. Do it now and use symbol names to make it easier to check and modify the dtsi in future. Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)