| Message ID | 20221215174942.2835690-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells | expand |
On 15/12/2022 18:49, Lucas Stach wrote: > The HSIO blk-ctrl has a internal PLL, which can be used as a reference > clock for the PCIe PHY. Add clock-cells to the binding to allow the > driver to expose this PLL. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi Lucas: > -----Original Message----- > From: Lucas Stach <l.stach@pengutronix.de> > Sent: 2022年12月16日 1:50 > To: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org>; Shawn Guo <shawnguo@kernel.org>; > Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: dl-linux-imx <linux-imx@nxp.com>; Pengutronix Kernel Team > <kernel@pengutronix.de>; Marcel Ziswiler <marcel.ziswiler@toradex.com>; > marex@denx.de; tharvey@gateworks.com; alexander.stein@ew.tq-group.com; > richard.leitner@linux.dev; lukas@mntre.com; patchwork-lst@pengutronix.de; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Subject: [PATCH v2 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells > > The HSIO blk-ctrl has a internal PLL, which can be used as a reference clock for > the PCIe PHY. Add clock-cells to the binding to allow the driver to expose this > PLL. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Thanks a lot for this series. Verified on i.MX8MP EVK board when internal PLL clock mode is enabled. Reviewed-and-Tested-by: Richard Zhu <hongxing.zhu@nxp.com> Best Regards Richard Zhu > --- > v2: fix clock-cells value > --- > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > index c29181a9745b..1fe68b53b1d8 100644 > --- > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl > +++ .yaml > @@ -39,6 +39,9 @@ properties: > - const: pcie > - const: pcie-phy > > + '#clock-cells': > + const: 0 > + > clocks: > minItems: 2 > maxItems: 2 > @@ -85,4 +88,5 @@ examples: > power-domain-names = "bus", "usb", "usb-phy1", > "usb-phy2", "pcie", "pcie-phy"; > #power-domain-cells = <1>; > + #clock-cells = <0>; > }; > -- > 2.30.2
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index c29181a9745b..1fe68b53b1d8 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -39,6 +39,9 @@ properties: - const: pcie - const: pcie-phy + '#clock-cells': + const: 0 + clocks: minItems: 2 maxItems: 2 @@ -85,4 +88,5 @@ examples: power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; #power-domain-cells = <1>; + #clock-cells = <0>; };
The HSIO blk-ctrl has a internal PLL, which can be used as a reference clock for the PCIe PHY. Add clock-cells to the binding to allow the driver to expose this PLL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- v2: fix clock-cells value --- .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ 1 file changed, 4 insertions(+)