| Message ID | 20221209111313.2701-3-fnkl.kernel@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PWM and keyboard backlight driver for ARM Macs | expand |
Hello, over all the driver looks good. Just a few smaller issues below. I wonder if it's a good idea to call this driver "apple". SoC vendors seem to reinvent their peripherals (or buy them somewhere else) for their different generations of processors. Maybe call it "apple-s5l" already today and not only when the next generation SoC appears? (I don't feel strong here, if you want to delay that renaming until there is an incompatible SoC that's fine for me.) On Fri, Dec 09, 2022 at 02:13:11PM +0300, Sasha Finkelstein wrote: > diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c > new file mode 100644 > index 000000000000..a85fecb20105 > --- /dev/null > +++ b/drivers/pwm/pwm-apple.c > @@ -0,0 +1,150 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Driver for the Apple SoC PWM controller > + * > + * Copyright The Asahi Linux Contributors > + * > + * Limitations: > + * - The writes to cycle registers are shadowed until a write to > + * the control register. > + */ > + > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/io.h> > +#include <linux/clk.h> > +#include <linux/pm_runtime.h> > +#include <linux/math64.h> I didn't test, but I think you don't need pm_runtime.h here. Also maybe the of headers are not needed? > +#define APPLE_PWM_CONTROL 0x00 > +#define APPLE_PWM_ON_CYCLES 0x1c > +#define APPLE_PWM_OFF_CYCLES 0x18 > + > +#define APPLE_CTRL_ENABLE BIT(0) > +#define APPLE_CTRL_MODE BIT(2) > +#define APPLE_CTRL_UPDATE BIT(5) > +#define APPLE_CTRL_TRIGGER BIT(9) > +#define APPLE_CTRL_INVERT BIT(10) > +#define APPLE_CTRL_OUTPUT_ENABLE BIT(14) Would be nice if the register prefix would match the register name. That is please either rename APPLE_PWM_CONTROL to APPLE_PWM_CTRL or use APPLE_PWM_CONTROL as prefix for the bit fields in that register. > + > +struct apple_pwm { > + struct pwm_chip chip; > + void __iomem *base; > + u64 clkrate; > +}; > + > +static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip) > +{ > + return container_of(chip, struct apple_pwm, chip); > +} > + > +static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > +{ > + struct apple_pwm *fpwm; > + u64 on_cycles, off_cycles; The declaration can move into the if block below. > + > + fpwm = to_apple_pwm(chip); > + if (state->enabled) { > + on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, > + state->duty_cycle, NSEC_PER_SEC); > + if (on_cycles > 0xFFFFFFFF) > + return -ERANGE; > + > + off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, > + state->period, NSEC_PER_SEC) - on_cycles; > + if (off_cycles > 0xFFFFFFFF) > + return -ERANGE; > + > + writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES); > + writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES); > + writel(APPLE_CTRL_ENABLE | APPLE_CTRL_OUTPUT_ENABLE | APPLE_CTRL_UPDATE, > + fpwm->base + APPLE_PWM_CONTROL); > + } else { > + writel(0, fpwm->base + APPLE_PWM_CONTROL); > + } > + return 0; Assuming clkrate = 24000000, I wonder what happens if (duty_cycle and) period are so small that on_cycles and off_cycles are both zero. How does the hardware behave in this case? > +} > + > +static void apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > + struct pwm_state *state) > +{ > + struct apple_pwm *fpwm; > + u32 on_cycles, off_cycles, ctrl; > + > + fpwm = to_apple_pwm(chip); > + > + ctrl = readl(fpwm->base + APPLE_PWM_CONTROL); > + on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES); > + off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES); > + > + state->enabled = (ctrl & APPLE_CTRL_ENABLE) && (ctrl & APPLE_CTRL_OUTPUT_ENABLE); > + state->polarity = PWM_POLARITY_NORMAL; > + state->duty_cycle = mul_u64_u64_div_u64(on_cycles, NSEC_PER_SEC, fpwm->clkrate); > + state->period = mul_u64_u64_div_u64(off_cycles + on_cycles, > + NSEC_PER_SEC, fpwm->clkrate); Wrong rounding direction, you need to round up. Did you test with PWM_DEBUG on? This should point out the more obvious cases. Assuming clkrate = 24000000 for example setting .duty_cycle = 3 should trigger a warning. Unfortunately there is no variant of mul_u64_u64_div_u64 that rounds up, maybe we need to introduce one. > +} Best regards Uwe
On Fri, Dec 09, 2022 at 02:13:11PM +0300, Sasha Finkelstein wrote: > Adds the Apple PWM controller driver. > > Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> > Acked-by: Sven Peter <sven@svenpeter.dev> > --- > drivers/pwm/Kconfig | 12 ++++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-apple.c | 150 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 163 insertions(+) > create mode 100644 drivers/pwm/pwm-apple.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 60d13a949bc5..c3be11468414 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -51,6 +51,18 @@ config PWM_AB8500 > To compile this driver as a module, choose M here: the module > will be called pwm-ab8500. > > +config PWM_APPLE > + tristate "Apple SoC PWM support" > + depends on ARCH_APPLE || COMPILE_TEST > + help > + Generic PWM framework driver for PWM controller present on > + Apple SoCs > + > + Say Y here if you have an ARM Apple laptop, otherwise say N > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-apple. > + > config PWM_ATMEL > tristate "Atmel PWM support" > depends on ARCH_AT91 || COMPILE_TEST > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 7bf1a29f02b8..19899b912e00 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -2,6 +2,7 @@ > obj-$(CONFIG_PWM) += core.o > obj-$(CONFIG_PWM_SYSFS) += sysfs.o > obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o > +obj-$(CONFIG_PWM_APPLE) += pwm-apple.o > obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o > obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o > obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o > diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c > new file mode 100644 > index 000000000000..a85fecb20105 > --- /dev/null > +++ b/drivers/pwm/pwm-apple.c > @@ -0,0 +1,150 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Driver for the Apple SoC PWM controller > + * > + * Copyright The Asahi Linux Contributors > + * > + * Limitations: > + * - The writes to cycle registers are shadowed until a write to > + * the control register. > + */ > + > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/io.h> > +#include <linux/clk.h> > +#include <linux/pm_runtime.h> > +#include <linux/math64.h> > + > +#define APPLE_PWM_CONTROL 0x00 > +#define APPLE_PWM_ON_CYCLES 0x1c > +#define APPLE_PWM_OFF_CYCLES 0x18 > + > +#define APPLE_CTRL_ENABLE BIT(0) > +#define APPLE_CTRL_MODE BIT(2) > +#define APPLE_CTRL_UPDATE BIT(5) > +#define APPLE_CTRL_TRIGGER BIT(9) > +#define APPLE_CTRL_INVERT BIT(10) > +#define APPLE_CTRL_OUTPUT_ENABLE BIT(14) > + > +struct apple_pwm { > + struct pwm_chip chip; > + void __iomem *base; > + u64 clkrate; > +}; > + > +static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip) > +{ > + return container_of(chip, struct apple_pwm, chip); > +} > + > +static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > +{ > + struct apple_pwm *fpwm; > + u64 on_cycles, off_cycles; > + polarity handling is missing here and in .get_state(). I assume you want: if (state->polarity == PWM_POLARITY_INVERSED) return -EINVAL; here and state->polarity = PWM_POLARITY_NORMAL; in .get_state(). > + fpwm = to_apple_pwm(chip); > + if (state->enabled) { > + on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, > + state->duty_cycle, NSEC_PER_SEC); > + if (on_cycles > 0xFFFFFFFF) > + return -ERANGE; > + > + off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, > + state->period, NSEC_PER_SEC) - on_cycles; > + if (off_cycles > 0xFFFFFFFF) > + return -ERANGE; > + > + writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES); > + writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES); > + writel(APPLE_CTRL_ENABLE | APPLE_CTRL_OUTPUT_ENABLE | APPLE_CTRL_UPDATE, > + fpwm->base + APPLE_PWM_CONTROL); > + } else { > + writel(0, fpwm->base + APPLE_PWM_CONTROL); > + } > + return 0; > +} Best regards Uwe
On 19/12/2022 22.06, Uwe Kleine-König wrote: > Hello, > > over all the driver looks good. Just a few smaller issues below. > > I wonder if it's a good idea to call this driver "apple". SoC vendors > seem to reinvent their peripherals (or buy them somewhere else) for > their different generations of processors. Maybe call it "apple-s5l" > already today and not only when the next generation SoC appears? > (I don't feel strong here, if you want to delay that renaming until > there is an incompatible SoC that's fine for me.) Well... considering s5l refers to the s5l8920x, the SoC used in the iPhone 3GS released in 2009, and here we are with the M1 13 years later and it's still the same, I think we're doing pretty well here. (Apple doesn't reinvent their peripherals nearly as often as other vendors). - Hector
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..c3be11468414 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -51,6 +51,18 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_APPLE + tristate "Apple SoC PWM support" + depends on ARCH_APPLE || COMPILE_TEST + help + Generic PWM framework driver for PWM controller present on + Apple SoCs + + Say Y here if you have an ARM Apple laptop, otherwise say N + + To compile this driver as a module, choose M here: the module + will be called pwm-apple. + config PWM_ATMEL tristate "Atmel PWM support" depends on ARCH_AT91 || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..19899b912e00 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_APPLE) += pwm-apple.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c new file mode 100644 index 000000000000..a85fecb20105 --- /dev/null +++ b/drivers/pwm/pwm-apple.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Driver for the Apple SoC PWM controller + * + * Copyright The Asahi Linux Contributors + * + * Limitations: + * - The writes to cycle registers are shadowed until a write to + * the control register. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/pm_runtime.h> +#include <linux/math64.h> + +#define APPLE_PWM_CONTROL 0x00 +#define APPLE_PWM_ON_CYCLES 0x1c +#define APPLE_PWM_OFF_CYCLES 0x18 + +#define APPLE_CTRL_ENABLE BIT(0) +#define APPLE_CTRL_MODE BIT(2) +#define APPLE_CTRL_UPDATE BIT(5) +#define APPLE_CTRL_TRIGGER BIT(9) +#define APPLE_CTRL_INVERT BIT(10) +#define APPLE_CTRL_OUTPUT_ENABLE BIT(14) + +struct apple_pwm { + struct pwm_chip chip; + void __iomem *base; + u64 clkrate; +}; + +static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct apple_pwm, chip); +} + +static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct apple_pwm *fpwm; + u64 on_cycles, off_cycles; + + fpwm = to_apple_pwm(chip); + if (state->enabled) { + on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->duty_cycle, NSEC_PER_SEC); + if (on_cycles > 0xFFFFFFFF) + return -ERANGE; + + off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->period, NSEC_PER_SEC) - on_cycles; + if (off_cycles > 0xFFFFFFFF) + return -ERANGE; + + writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES); + writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES); + writel(APPLE_CTRL_ENABLE | APPLE_CTRL_OUTPUT_ENABLE | APPLE_CTRL_UPDATE, + fpwm->base + APPLE_PWM_CONTROL); + } else { + writel(0, fpwm->base + APPLE_PWM_CONTROL); + } + return 0; +} + +static void apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct apple_pwm *fpwm; + u32 on_cycles, off_cycles, ctrl; + + fpwm = to_apple_pwm(chip); + + ctrl = readl(fpwm->base + APPLE_PWM_CONTROL); + on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES); + off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES); + + state->enabled = (ctrl & APPLE_CTRL_ENABLE) && (ctrl & APPLE_CTRL_OUTPUT_ENABLE); + state->polarity = PWM_POLARITY_NORMAL; + state->duty_cycle = mul_u64_u64_div_u64(on_cycles, NSEC_PER_SEC, fpwm->clkrate); + state->period = mul_u64_u64_div_u64(off_cycles + on_cycles, + NSEC_PER_SEC, fpwm->clkrate); +} + +static const struct pwm_ops apple_pwm_ops = { + .apply = apple_pwm_apply, + .get_state = apple_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int apple_pwm_probe(struct platform_device *pdev) +{ + struct apple_pwm *fpwm; + struct clk *clk; + int ret; + + fpwm = devm_kzalloc(&pdev->dev, sizeof(*fpwm), GFP_KERNEL); + if (!fpwm) + return -ENOMEM; + + fpwm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(fpwm->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(fpwm->base), "unable to map mmio"); + + clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock"); + + /* + * uses the 24MHz system clock on all existing devices, can only + * happen if the device tree is broken + */ + fpwm->clkrate = clk_get_rate(clk); + if (fpwm->clkrate > NSEC_PER_SEC) + return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range"); + + fpwm->chip.dev = &pdev->dev; + fpwm->chip.npwm = 1; + fpwm->chip.ops = &apple_pwm_ops; + + ret = devm_pwmchip_add(&pdev->dev, &fpwm->chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip"); + + return 0; +} + +static const struct of_device_id apple_pwm_of_match[] = { + { .compatible = "apple,s5l-fpwm" }, + {} +}; +MODULE_DEVICE_TABLE(of, apple_pwm_of_match); + +static struct platform_driver apple_pwm_driver = { + .probe = apple_pwm_probe, + .driver = { + .name = "apple-pwm", + .of_match_table = apple_pwm_of_match, + }, +}; +module_platform_driver(apple_pwm_driver); + +MODULE_DESCRIPTION("Apple SoC PWM driver"); +MODULE_LICENSE("Dual MIT/GPL");