| Message ID | 20221221170003.2929-1-shentey@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | This series consolidates the implementations of the PIIX3 and PIIX4 south | expand |
On 21/12/22 17:59, Bernhard Beschow wrote: > code as possible and to bring both device models to feature parity such that > perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This > could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this > list before. > > The series is structured as follows: First, PIIX3 is changed to instantiate > internal devices itself, like PIIX4 does already. Second, PIIX3 gets prepared > for the merge with PIIX4 which includes some fixes, cleanups, and renamings. > Third, the same is done for PIIX4. In step four the implementations are merged. > Since some consolidations could be done easier with merged implementations, the > consolidation continues in step five which concludes the series. > > One particular challenge in this series was that the PIC of PIIX3 used to be > instantiated outside of the south bridge while some sub functions require a PIC > with populated qemu_irqs. This has been solved by introducing a proxy PIC which > furthermore allows PIIX3 to be agnostic towards the virtualization technology > used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the proxy PIC as well. > > Another challenge was dealing with optional devices where Peter already gave > advice in [1] which this series implements. > > Last but not least there might be some opportunity to consolidate VM state > handling, probably by reusing the one from PIIX3. Since I'm not very familiar > with the requirements I didn't touch it so far. > > v4: > - Rebase onto "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" > since it is already queued via mips-next. This eliminates patches > 'hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"' and 'hw/isa/piix4: > Prefix pci_slot_get_pirq() with "piix4_"'. > - Squash 'hw/isa/piix: Drop the "3" from the PIIX base class' into > 'hw/isa/piix3: Rename typedef PIIX3State to PIIXState'. I originally only > split these patches since I wasn't sure whether renaming a type was allowed. > - Add new patch 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is > created' for forther cleanup of INTx-to-LNKx route decoupling. Sigh I did the rebase this morning and was waiting for the test suite... https://gitlab.com/philmd/qemu/-/commits/mips-testing/ Anyway I'll double-check with this series.
Am 21. Dezember 2022 19:15:04 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >On 21/12/22 17:59, Bernhard Beschow wrote: >> code as possible and to bring both device models to feature parity such that >> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >> list before. >> >> The series is structured as follows: First, PIIX3 is changed to instantiate >> internal devices itself, like PIIX4 does already. Second, PIIX3 gets prepared >> for the merge with PIIX4 which includes some fixes, cleanups, and renamings. >> Third, the same is done for PIIX4. In step four the implementations are merged. >> Since some consolidations could be done easier with merged implementations, the >> consolidation continues in step five which concludes the series. >> >> One particular challenge in this series was that the PIC of PIIX3 used to be >> instantiated outside of the south bridge while some sub functions require a PIC >> with populated qemu_irqs. This has been solved by introducing a proxy PIC which >> furthermore allows PIIX3 to be agnostic towards the virtualization technology >> used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the proxy PIC as well. >> >> Another challenge was dealing with optional devices where Peter already gave >> advice in [1] which this series implements. >> >> Last but not least there might be some opportunity to consolidate VM state >> handling, probably by reusing the one from PIIX3. Since I'm not very familiar >> with the requirements I didn't touch it so far. >> >> v4: >> - Rebase onto "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" >> since it is already queued via mips-next. This eliminates patches >> 'hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"' and 'hw/isa/piix4: >> Prefix pci_slot_get_pirq() with "piix4_"'. >> - Squash 'hw/isa/piix: Drop the "3" from the PIIX base class' into >> 'hw/isa/piix3: Rename typedef PIIX3State to PIIXState'. I originally only >> split these patches since I wasn't sure whether renaming a type was allowed. >> - Add new patch 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is >> created' for forther cleanup of INTx-to-LNKx route decoupling. > >Sigh I did the rebase this morning and was waiting for the test suite... >https://gitlab.com/philmd/qemu/-/commits/mips-testing/ Hmm, I'm a little confused. I thought to do the rebase myself in order to help which I announced yesterday. AFAICS the nanoMIPS bootloader still needs to be adapted before this series can be queued and tested. Let me know if I could help. >Anyway I'll double-check with this series. Thank you! Best regards, Bernhard
code as possible and to bring both device models to feature parity such that perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this list before. The series is structured as follows: First, PIIX3 is changed to instantiate internal devices itself, like PIIX4 does already. Second, PIIX3 gets prepared for the merge with PIIX4 which includes some fixes, cleanups, and renamings. Third, the same is done for PIIX4. In step four the implementations are merged. Since some consolidations could be done easier with merged implementations, the consolidation continues in step five which concludes the series. One particular challenge in this series was that the PIC of PIIX3 used to be instantiated outside of the south bridge while some sub functions require a PIC with populated qemu_irqs. This has been solved by introducing a proxy PIC which furthermore allows PIIX3 to be agnostic towards the virtualization technology used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the proxy PIC as well. Another challenge was dealing with optional devices where Peter already gave advice in [1] which this series implements. Last but not least there might be some opportunity to consolidate VM state handling, probably by reusing the one from PIIX3. Since I'm not very familiar with the requirements I didn't touch it so far. v4: - Rebase onto "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" since it is already queued via mips-next. This eliminates patches 'hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"' and 'hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_"'. - Squash 'hw/isa/piix: Drop the "3" from the PIIX base class' into 'hw/isa/piix3: Rename typedef PIIX3State to PIIXState'. I originally only split these patches since I wasn't sure whether renaming a type was allowed. - Add new patch 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created' for forther cleanup of INTx-to-LNKx route decoupling. Testing done: * make check * make check-avocado * Boot live CD: * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * 'qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=ttyS0"` Based-on: <20221120150550.63059-1-shentey@gmail.com> "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" v3: - Introduce one TYPE_ICH9_USB_UHCI(fn) rather than several TYPE_ICH9_USB_UHCIx (Philippe) - Make proxy PIC generic (Philippe) - Track Malta's PIIX dependencies through KConfig - Rebase onto Philippe's 'hw/isa/piix4: Remove MIPS Malta specific bits' series [3] - Also rebase onto latest master to resolve merge conflicts. This required copying Philippe's series as first three patches - please ignore. v2: - Introduce TYPE_ defines for IDE and USB device models (Mark) - Omit unexporting of PIIXState (Mark) - Improve commit message of patch 5 to mention reset triggering through PCI configuration space (Mark) - Move reviewed patches w/o dependencies to the bottom of the series for early upstreaming [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html [2] https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03310.html [3] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg05367.html Bernhard Beschow (27): hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge hw/i386/pc: Create RTC controllers in south bridges hw/i386/pc: No need for rtc_state to be an out-parameter hw/isa/piix3: Create USB controller in host device hw/isa/piix3: Create power management controller in host device hw/core: Introduce proxy-pic hw/isa/piix3: Create Proxy PIC in host device hw/isa/piix3: Create IDE controller in host device hw/isa/piix3: Wire up ACPI interrupt internally hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 hw/isa/piix3: Drop the "3" from PIIX base class hw/isa/piix4: Make PIIX4's ACPI and USB functions optional hw/isa/piix4: Remove unused inbound ISA interrupt lines hw/isa/piix4: Use Proxy PIC device hw/isa/piix4: Reuse struct PIIXState from PIIX3 hw/isa/piix4: Rename reset control operations to match PIIX3 hw/isa/piix3: Merge hw/isa/piix4.c hw/isa/piix: Harmonize names of reset control memory regions hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Rename functions to be shared for interrupt triggering hw/isa/piix: Consolidate IRQ triggering hw/isa/piix: Share PIIX3's base class with PIIX4 Philippe Mathieu-Daudé (3): hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader hw/isa/piix4: Correct IRQRC[A:D] reset values MAINTAINERS | 8 +- configs/devices/mips-softmmu/common.mak | 2 - hw/core/Kconfig | 3 + hw/core/meson.build | 1 + hw/core/proxy-pic.c | 70 ++++++ hw/i386/Kconfig | 4 +- hw/i386/pc.c | 16 +- hw/i386/pc_piix.c | 77 +++--- hw/i386/pc_q35.c | 16 +- hw/isa/Kconfig | 10 +- hw/isa/lpc_ich9.c | 8 + hw/isa/meson.build | 3 +- hw/isa/{piix3.c => piix.c} | 274 ++++++++++++++++----- hw/isa/piix4.c | 302 ------------------------ hw/mips/Kconfig | 2 + hw/mips/malta.c | 38 ++- hw/usb/hcd-uhci.c | 16 +- hw/usb/hcd-uhci.h | 4 + include/hw/core/proxy-pic.h | 54 +++++ include/hw/i386/ich9.h | 2 + include/hw/i386/pc.h | 2 +- include/hw/southbridge/piix.h | 30 ++- 22 files changed, 496 insertions(+), 446 deletions(-) create mode 100644 hw/core/proxy-pic.c rename hw/isa/{piix3.c => piix.c} (57%) delete mode 100644 hw/isa/piix4.c create mode 100644 include/hw/core/proxy-pic.h